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DM504 Datasheet(PDF) 3 Page - Texas Instruments |
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DM504 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 211 page  SPRS917_Intro_001 JTAG PLLs OSC Clock Comparator (DCC ) x7 Error Handler (ESM) TESOC (LBIST/PBIST) CRC x1 RTI x5 Memory Controllers LPDDR2 32b Data or optinal 16b Data with ECC Timer x8 Mailbox/Spinlock 10-bit ADC Control Module Safety EDMA GPIO x4 PWMSSx1 MMUx1 System I2C x2 SPI x4 QSPI x1 SDIO x1 UART x3 McASP x3 Serial Interfaces GMAC Connectivity EDMA 2TC L2 256KB Cache C66x L1D 32KB L1P 32KB DSP Subsystem Video Input Port CAL LVDSRX CSI2 ISP Video Front End up to 512KB RAM with ECC IPU with ECC Dual Cortex M4 32KB ROM EVE 16MAC EDMA 2TC Vision Accelerator OSD Resizing CSC SD-DAC DVOUT Display Subsystem Interconnect DM504 Copyright © 2016, Texas Instruments Incorporated DCAN with ECC MCAN with FD PRCM 3 DM504 www.ti.com SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 Submit Documentation Feedback Device Overview Copyright © 2016–2017, Texas Instruments Incorporated 1.4 Functional Block Diagram Figure 1-1 is functional block diagram of the superset. Figure 1-1. DM504 Block Diagram |
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