DM504 datasheet(95/211 Pages) TI1

95 / 211 page

xi_osc1

CK0

CK1

SPRS91v_CLK_07

DM504

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SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Specifications

Figure 5-12. xi_osc1 Input Clock

5.9.4.1.4 RC On-die Oscillator Clock

RCOSC_32K_CLK is received directly through a network of resistor and capacitor (an RC network) inside

of the SoC. This RC oscillator do not have good frequency stability. The Frequency range is described in

Table 5-26, which depends on the temperature. For more information about RCOSC_32K_CLK see the

Device TRM, Chapter: Power, Reset, and Clock Management.

Table 5-26. RC On-die Oscillator Clock Frequency Range

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

RCOSC_32K_CLK

Internal RC Oscillator

Range from 28 to 42

kHz

5.9.4.2

Output Clocks

NOTE

NOTE TO USERS:

The content of this section is UNDER DEVELOPMENT!

5.9.4.3

DPLLs, DLLs

NOTE

For more information, see:

•

Power, Reset, and Clock Management / Clock Management Functional Description /

Internal Clock Sources/Generators / Generic DPLL Overview Section

and

•

Display Subsystem / Display Subsystem Overview section of the Device TRM.

To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the

PRCM module. They are of two types: type A and type B DPLLs.

•

They have their own independent power domain (each one embeds its own switch and can be

controlled as an independent functional power domain)

•

They are fed with ALWAYS ON system clock, with independent control per DPLL.

The different DPLLs managed by the PRCM are listed below:

•

DPLL_CORE: It supplies all interface clocks and also few module functional clocks.

•

DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock, a

96-MHz functional clock to subsystems and peripherals.

•

DPLL_GMAC_DSP: It supplies RGMII, EVE1 and DSP0 module functional clocks.

•

DPLL_EVE_VID_DSP: It provides a few module functional clocks (EVE_GFCLK, VID_PIX_CLK

and DSP1_CLK).

•

DPLL_DDR: It generates clocks for the one External Memory Interface (EMIF) controller and its

associated EMIF PHYs.

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