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DM504 Datasheet(PDF) 14 Page - Texas Instruments |
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DM504 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 211 page  Copyright © 2016–2017, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback 14 DM504 SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 www.ti.com Table 4-1. Pin Attributes(1) (continued) BALL NUMBER BOTTOM [1] BALL NUMBER TOP [2] BALL NAME [3] SIGNAL NAME [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET REL. MUXMODE [9] I/O VOLTAGE VALUE [10] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] N23 ddr1_dqm0 ddr1_dqm0 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy L23 ddr1_dqm1 ddr1_dqm1 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy AB20 ddr1_dqm2 ddr1_dqm2 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy B20 ddr1_dqm3 ddr1_dqm3 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy R23 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy J22 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy AB18 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy B18 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy P22 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy K23 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy AC19 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy A19 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy M22 ddr1_ext_vref0 ddr1_ext_vref0 0 PWR OFF OFF 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy P2 ddr1_ext_vref1 ddr1_ext_vref1 0 PWR OFF OFF 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy Y1 ddr1_nck ddr1_nck 0 O PD drive clk (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy N17 adc_in0 adc_in0 0 A 15 1.8 vdda_adc NA GPADC NA N16 adc_in1 adc_in1 0 A 15 1.8 vdda_adc NA GPADC NA N15 adc_in2 adc_in2 0 A 15 1.8 vdda_adc NA GPADC NA P17 adc_in3 adc_in3 0 A 15 1.8 vdda_adc NA GPADC NA P16 adc_in4 adc_in4 0 A 15 1.8 vdda_adc NA GPADC NA M15 adc_in5 adc_in5 0 A 15 1.8 vdda_adc NA GPADC NA L17 adc_in6 adc_in6 0 A 15 1.8 vdda_adc NA GPADC NA M14 adc_in7 adc_in7 0 A 15 1.8 vdda_adc NA GPADC NA L16 adc_vrefp adc_vrefp 0 A 15 1.8 vdda_adc NA GPADC NA K12 cap_vddram_core1 cap_vddram_core1 CAP J10 cap_vddram_core2 cap_vddram_core2 CAP J9 cap_vddram_dspeve cap_vddram_dspeve CAP |
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