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DM504 Datasheet(PDF) 50 Page - Texas Instruments |
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DM504 Datasheet(HTML) 50 Page - Texas Instruments |
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50 / 211 page ![]() 50 DM504 SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 www.ti.com Submit Documentation Feedback Terminal Configuration and Functions Copyright © 2016–2017, Texas Instruments Incorporated Table 4-23. PRCM Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL rstoutn Reset out (Active low). This pin asserts low in response to any global reset condition on the device. O E3 resetn Device Reset I E2 porz Power on Reset (active low). This pin must be asserted low until all device supplies are valid (see reset sequence/requirements). I E1 xref_clk0 External Reference Clock 0. For Audio and other Peripherals. I R2 xref_clk1 External Reference Clock 1. For Audio and other Peripherals. I C5, C6 xref_clk2 External Reference Clock 2. For Audio and other Peripherals. I H15 xi_osc0 System Oscillator OSC0 Crystal input / LVCMOS clock input. Functions as the input connection to a crystal when the internal oscillator OSC0 is used. Functions as an LVCMOS-compatible input clock when an external oscillator is used. I E16 xi_osc1 Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input. Functions as the input connection to a crystal when the internal oscillator OSC1 is used. Functions as an LVCMOS-compatible input clock when an external oscillator is used I C17 xo_osc0 System Oscillator OSC0 Crystal output O D16 xo_osc1 Auxiliary Oscillator OSC1 Crystal output O D17 4.3.21.3 Interrupt Controllers (INTC) NOTE For more information, see the Interrupt Controllers section of the device TRM. Table 4-24. INTC Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL nmin Non maskable interrupt input - active-low. This pin can be optionally routed to the DSP NMI input or as generic input to the ARM cores. I F3 sys_nirq1 External interrupt event to any device INTC I K17, L15 sys_nirq2 External interrupt event to any device INTC I K15, K16 esm_error This signal indicates a severe device failure. For more information see Error Signaling Module in the device TRM. IO C13 , R10 4.3.22 Power Supplies NOTE For more information, see Power, Reset, and Clock Management / PRCM Subsystem Environment / External Voltage Inputs section of the device TRM. Table 4-25. Power Supply Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BOTTOM BALL TOP BALL vdd Core voltage domain supply PWR F7, H12, J6, J12, L13, N5, N8 vss Ground GND A1, A17, B13, E10, F6, F8, F9, F10, G12, G13, H7, H8, H9, H10, H11, J11, K1, K5, K6, L5, L7, L8, L11, L12, M5, M8, M10, M13, P11, U1, U2, U16 A12, A15, A18, A21, AA1, B10, B5, B8, C1, C23, F2, F23, J2, J23, M2, M23, P23 , R1, U23, V1, Y23 vdd_dspeve EVE-DSP voltage domain supply PWR H6, L6, L9, L10, M6 |
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