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DM504 Datasheet(PDF) 42 Page - Texas Instruments |
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DM504 Datasheet(HTML) 42 Page - Texas Instruments |
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42 / 211 page  42 DM504 SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 www.ti.com Submit Documentation Feedback Terminal Configuration and Functions Copyright © 2016–2017, Texas Instruments Incorporated Table 4-13. SPI Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL spi1_d1 SPI1 Data. Can be configured as either MISO or MOSI. IO R3 spi1_cs0 SPI1 Chip Select IO N3, R2 spi1_cs1 SPI1 Chip Select IO N2, R2 spi1_cs2 SPI1 Chip Select IO C5, T2 spi1_cs3 SPI1 Chip Select IO D7, T3 Serial Peripheral Interface 2 spi2_sclk SPI2 Clock IO M2 spi2_d0 SPI2 Data. Can be configured as either MISO or MOSI. IO L2 spi2_d1 SPI2 Data. Can be configured as either MISO or MOSI. IO M3 spi2_cs0 SPI2 Chip Select IO L3 spi2_cs1 SPI2 Chip Select IO R2 Serial Peripheral Interface 3 spi3_sclk SPI3 Clock IO C6 spi3_d0 SPI3 Data. Can be configured as either MISO or MOSI. IO C8 spi3_d1 SPI3 Data. Can be configured as either MISO or MOSI. IO E6 spi3_cs0 SPI3 Chip Select IO C9, R2 spi3_cs1 SPI3 Chip Select IO N2 Serial Peripheral Interface 4 spi4_sclk SPI4 Clock IO C12, C5 spi4_d0 SPI4 Data. Can be configured as either MISO or MOSI. IO C13, D6 spi4_d1 SPI4 Data. Can be configured as either MISO or MOSI. IO B14, B4 spi4_cs0 SPI4 Chip Select IO D12, D7 4.3.13 QSPI NOTE For more information see the Serial Communication Interface / Quad Serial Peripheral Interface section of the device TRM. CAUTION The IO timings provided in Section 5.9 Timing Requirements and Switching Characteristics are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 5-45. Table 4-14. QSPI Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BOTTOM BALL TOP BALL qspi1_sclk QSPI1 Serial Clock O C1 K1 qspi1_rtclk QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer to PCB Guidelines for QSPI1 I B4, D7 qspi1_d0 QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read and quad read modes it becomes input data pin during read phase. IO C3 H2 qspi1_d1 QSPI1 Data[1]. Input read data in all modes. IO C2 H1 qspi1_d2 QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during read phase IO B3 G2 qspi1_d3 QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during read phase IO A3 G1 |
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