DM504 datasheet(92/211 Pages) TI1

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CL=

C C

(C +C )

xi_osc1

vssa_osc1

Device

xo_osc1

Crystal

(Optional)

SPRS91v_CLK_05

xi_osc0

CK0

CK1

SPRS91v_CLK_04

DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Specifications

Table 5-21. OSC0 Input Clock Timing Requirements (continued)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

tj(xiosc0)

Frequency accuracy(2), xi_osc0

Ethernet not used

±200

ppm

Ethernet RGMII using

derived clock

±50

ppm

(1) Period jitter is meant here as follows:

– The maximum value is the difference between the longest measured clock period and the expected clock period

– The minimum value is the difference between the shortest measured clock period and the expected clock period

(2) Crystal characteristics should account for tolerance+stability+aging.

Figure 5-8. xi_osc0 Input Clock

5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock

SYS_CLK2 is received directly from oscillator OSC1. For more information about SYS_CLK2 see Device

TRM, Chapter: Power, Reset, and Clock Management.

5.9.4.1.3.1 OSC1 External Crystal

An external crystal is connected to the device pins. Figure 5-9 describes the crystal implementation.

Figure 5-9. Crystal Implementation

NOTE

The load capacitors, Cf1 and Cf2 in Figure 5-9, should be chosen such that the below

equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All

discrete components used to implement the oscillator circuit should be placed as close as

possible to the associated oscillator xi_osc1, xo_osc1, and vssa_osc1 pins.

Figure 5-10. Load capacitance equation

DM504 Datasheet(PDF) 92 Page - Texas Instruments

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