DM504 datasheet(96/211 Pages) TI1

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DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Specifications

NOTE

The following DPLLs are controlled by the clock manager located in the always-on Core

power domain (CM_CORE_AON):

•

DPLL_CORE, DPLL_DDR, DPLL_GMAC_DSP, DPLL_PER, DPLL_EVE_VID_DSP.

For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and

Clock Management (PRCM) chapter of the Device TRM.

5.9.4.3.1 DPLL Characteristics

The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated

the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass

mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when

selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next

paragraph.

The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and

CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are

generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,

CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with

the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through

an asynchronous multplexing.

For more information, see the Power, Reset, and Clock Management chapter of the Device TRM.

Table 5-27 summarizes DPLL type described in Section 5.9.4.3, DPLLs, DLLs Specifications.

Table 5-27. DPLL Control Type

DPLL NAME

TYPE

CONTROLLED BY PRCM

DPLL_CORE

Table 5-28 (Type A)

Yes(1)

DPLL_EVE_VID_DSP

Table 5-28 (Type A)

Yes(1)

DPLL_GMAC_DSP

Table 5-28 (Type A)

Yes(1)

DPLL_PER

Table 5-28 (Type A)

Yes(1)

DPLL_DDR

Table 5-28 (Type A)

Yes(1)

(1) DPLL is in the always-on domain.

Table 5-28 and summarize the DPLL characteristics and assume testing over recommended operating

conditions.

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