DM504 datasheet(66/211 Pages) TI1

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DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Specifications

Table 5-2. AVS Requirements per vdd_* Supply (continued)

Supply

AVS Required?

vdd_dspeve

Yes, for all OPPs

5.5.2

Voltage And Core Clock Specifications

Table 5-3 shows the recommended OPP per voltage domain.

Table 5-3. Voltage Domains Operating Performance Points

DOMAIN

CONDITION

OPP_NOM

OPP_OD

OPP_HIGH

MIN (2)

NOM (1)

MAX (2)

MIN (2)

NOM (1)

MAX (2)

MIN (2)

NOM (1)

MAX DC (3)

MAX (2)

VD_CORE (V)

BOOT (Before

AVS is

enabled) (4)

1.11

1.15

1.20

Not Applicable

After AVS is

enabled (4)

AVS

Voltage

(5) –

3.5%

AVS

Voltage

(5)

1.20

Not Applicable

VD_DSPEVE (V)

BOOT (Before

AVS is

enabled) (4)

1.11

1.15

1.20

Not Applicable

After AVS is

enabled (4)

AVS

Voltage

(5) –

3.5%

AVS

Voltage

(5)

1.20

Not Applicable

(1) In a typical implementation, the power supply should target the NOM voltage.

(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This

requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.

(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH

(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.

(4) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.

(5) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the

STD_FUSE_OPP. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the TRM.

The power supply should be adjustable over the following ranges for each required OPP:

–

OPP_NOM: 0.85V - 1.15V

–

OPP_OD: 0.94V - 1.15V

–

OPP_HIGH: 1.05V - 1.25V

The AVS Voltages will be within the above specified ranges.

Table 5-4 describes the standard processor clocks speed characteristics vs OPP of the device.

Table 5-4. Supported OPP vs Max Frequency(2)

DESCRIPTION

OPP_NOM

OPP_OD

OPP_HIGH

Max Freq. (MHz)

VD_DSPEVE

DSP_CLK

355

N/A

EVE_FCLK

355

N/A

VD_CORE

CORE_IPU1_CLK

212.8

N/A

L3_CLK

266

N/A

LPDDR2

400 (DDR2-800)

N/A

ADC

N/A

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