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DM504 Datasheet(PDF) 12 Page - Texas Instruments |
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DM504 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 211 page  Copyright © 2016–2017, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback 12 DM504 SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 www.ti.com Table 4-1. Pin Attributes(1) BALL NUMBER BOTTOM [1] BALL NUMBER TOP [2] BALL NAME [3] SIGNAL NAME [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET REL. MUXMODE [9] I/O VOLTAGE VALUE [10] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] AC6 ddr1_ca0 ddr1_ca0 0 O PD drive 1 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy AB6 ddr1_ca1 ddr1_ca1 0 O PD drive 1 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy AC7 ddr1_ca2 ddr1_ca2 0 O PD drive 1 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy AB8 ddr1_ca3 ddr1_ca3 0 O PD drive 1 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy AB9 ddr1_ca4 ddr1_ca4 0 O PD drive 1 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy W1 ddr1_ca5 ddr1_ca5 0 O PD drive 1 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy V2 ddr1_ca6 ddr1_ca6 0 O PD drive 1 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy U1 ddr1_ca7 ddr1_ca7 0 O PD drive 1 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy T2 ddr1_ca8 ddr1_ca8 0 O PD drive 1 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy T1 ddr1_ca9 ddr1_ca9 0 O PD drive 1 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy Y2 ddr1_ck ddr1_ck 0 O PD drive clk (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy AC3 ddr1_cke0 ddr1_cke0 0 O PD drive 0 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy AB3 ddr1_csn0 ddr1_csn0 0 O PD drive 1 (OFF) 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy AA23 ddr1_d0 ddr1_d0 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy Y22 ddr1_d1 ddr1_d1 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy W22 ddr1_d2 ddr1_d2 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy W23 ddr1_d3 ddr1_d3 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy V23 ddr1_d4 ddr1_d4 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy U22 ddr1_d5 ddr1_d5 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy T22 ddr1_d6 ddr1_d6 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy T23 ddr1_d7 ddr1_d7 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy H22 ddr1_d8 ddr1_d8 0 IO PD PD 1.2 vdds_ddr NA LVCMOS DDR PUx/PDy |
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