DM504 datasheet(38/211 Pages) TI1

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DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Terminal Configuration and Functions

Table 4-7. CPI Signal Descriptions (continued)

SIGNAL NAME

DESCRIPTION

TYPE

cpi_data13

Camera parallel data 13

K17

4.3.7

CSI2

NOTE

For more information, see the Imaging Subsystem chapter of the device TRM.

CAUTION

The IO timings provided in Section 5.9 Timing Requirements and Switching

Characteristics are only valid if signals within a single IOSET are used. The

IOSETs are defined in Table 5-34.

Table 4-8. CSI 2 Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

csi2_0_dx0

Serial Differential data/clock positive input - lane 0 (position 1)

csi2_0_dy0

Serial Differential data/clock negative input - lane 0 (position 1)

csi2_0_dx1

Serial Differential data/clock positive input - lane 1 (position 2)

csi2_0_dy1

Serial Differential data/clock negative input - lane 1 (position 2)

csi2_0_dx2

Serial Differential data/clock positive input - lane 2 (position 3)

csi2_0_dy2

Serial Differential data/clock negative input - lane 2 (position 3)

csi2_0_dx3

Serial Differential data/clock positive input - lane 3 (position 4)

A10

csi2_0_dy3

Serial Differential data/clock negative input - lane 3 (position 4)

B10

csi2_0_dx4

Serial Differential data positive input only - lane 4 (position 5) (1)

A11

csi2_0_dy4

Serial Differential data negative input only - lane 4 (position 5) (1)

B11

(1) Lane 4 (position 5) supports only data. For more information see Imaging Subsystem of the device TRM.

4.3.8

EMIF

NOTE

For more information, see the Memory Subsystem / EMIF1 Controller section of the device

TRM.

NOTE

The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in Table 4-9,

EMIF1 Signal Descriptions, column "SIGNAL NAME" is not to be confused with DDR1 type

of SDRAM memories.

Table 4-9. EMIF1 Signal Descriptions

SIGNAL

NAME

DESCRIPTION

TYPE

BOTTOM BALL

TOP BALL

ddr1_ca0

EMIF1 command / address bit 0

AC6

ddr1_ca1

EMIF1 command / address bit 1

AB6

ddr1_ca2

EMIF1 command / address bit 2

AC7

ddr1_ca3

EMIF1 command / address bit 3

AB8

ddr1_ca4

EMIF1 command / address bit 4

AB9

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