ELANSC520 datasheet(101/440 Pages) AMD

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SDRAM Controller Registers

Élan™SC520 Microcontroller Register Set Manual

7-13

If there is an ECC mismatch, either a single-bit or multiple-bit error has been detected. Single-bit errors are corrected

as data is returned to the requesting master (and an interrupt is generated if enabled). Multi-bit errors are not

corrected, but an NMI is generated if enabled.

This register (ECCCKTEST) provides a way for the user to alter the ECC check code that is written to the ECC

SDRAM. If the ECC check code is altered so that it reflects a single-bit or multiple-bit error, it is detected by the

ÉlanSC520 microcontroller when that location is read (if ECC is enabled). This feature can be used for test purposes

and also for ECC error-handler development.

Because the write buffer decouples master write requests from the actual SDRAM access, it is advisable to disable

the write buffer when using the feature provided by this register. Otherwise, the ECC check code specified in this

care should be taken to ensure that the Am5x86 CPU cache allows the write cycle to propagate to the SDRAM.

So that test software need not reproduce the ECC algorithm, Table 7-2 provides a few example ECC check codes

that are correct for the associated data.

Table 7-2

Example ECC Check Codes and Associated Data

32-Bit Data Write (Hexadecimal)

Correct ECC Check Code (Binary)

00000000

0000000

FFFFFFFF

0000000

000000BC

1111111

A5A5A5A5

1100011

C0C0C0C0

0101110

00AB0000

1001100

00BC0000

0100000

ELANSC520 Datasheet(PDF) 101 Page - Advanced Micro Devices