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ELANSC520 Datasheet(PDF) 162 Page - Advanced Micro Devices |
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ELANSC520 Datasheet(HTML) 162 Page - Advanced Micro Devices |
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162 / 440 page ![]() GP DMA Controller Registers 11-30 Élan™SC520 Microcontroller Register Set Manual GP-DMA Channel 6 Next Address Low (GPDMANXTADDL6) Memory-Mapped MMCR Offset DA8h Register Description This register provides address bits A15–A0 of the next memory address for Channel 6 in buffer chaining mode. Bit Definitions Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). Bit 0 of this register (GPDMANXTADDL6) is ignored for 16-bit mode transfers, so the buffer address used is always even in 16-bit mode. Software should ensure that 16-bit mode buffers always begin on an even word boundary. 15 14 13 12 11 10 9 8 Bit DMA6_NXT_ADR[15 –8] Reset 00000000 R/W R/W 7 6 5 4 3 2 1 0 Bit DMA6_NXT_ADR[7 –0] Reset 00000000 R/W R/W Bit Name Function 15–0 DMA6_NXT_ ADR[15 –0] DMA Channel 6 Next Address Low This bit field provides address bits A15–A0 of the next memory buffer to be used by Channel 6 in the buffer chaining mode. |
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