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ELANSC520 Datasheet(PDF) 159 Page - Advanced Micro Devices |
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ELANSC520 Datasheet(HTML) 159 Page - Advanced Micro Devices |
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159 / 440 page  GP DMA Controller Registers Élan™SC520 Microcontroller Register Set Manual 11-27 GP-DMA Channel 3 Next Address High (GPDMANXTADDH3) Memory-Mapped MMCR Offset DA2h Register Description This register provides address bits A27–A16 of the next memory address for Channel 3 in buffer chaining mode. Bit Definitions Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). 15 14 13 12 11 10 9 8 Bit Reserved DMA3_NXT_ADR[27 –24] Reset 00000000 R/W RSV R/W 7 6 5 4 3 2 1 0 Bit DMA3_NXT_ADR[23 –16] Reset 00000000 R/W R/W Bit Name Function 15 –12 Reserved Reserved This bit field should be written to 0 for normal system operation. 11–0 DMA3_NXT_ ADR[27 –16] DMA Channel 3 Next Address High This bit field provides address bits A27–A16 of the next memory buffer to be used by Channel 3 in the buffer chaining mode. |
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