ELANSC520 datasheet(157/440 Pages) AMD

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GP DMA Controller Registers

Élan™SC520 Microcontroller Register Set Manual

11-25

Buffer Chaining Valid (GPDMABCVAL)

Memory-Mapped

MMCR Offset D9Bh

This register provides the operating interface with the buffer chaining feature.

Bit Definitions

Programming Notes

A channel’s CHx_CBUF_VAL bit is ignored if buffer chaining is not enabled for the channel. Buffer chaining is enabled

separately for each channel in the GPDMABCCTL register (see page 11-21).

If buffer chaining is enabled for a channel, and if the channel’s CHx_CBUF_VAL bit is set when the end of the buffer

is reached (i.e., when the channel’s Transfer Count register reaches 0), then the channel’s Memory Address and

Transfer Count registers are loaded with the values in the channel’s Next Address and Next Count registers,

respectively. Then the channel’s CHx_CBUF_VAL bit is cleared by the GP bus DMA controller. An interrupt is also

generated if the CHx_INT_ENB bit is set in the GPDMABSINTENB register (see page 11-24).

If buffer chaining is enabled and software has not set the channel’s CHx_CBUF_VAL bit before the end of the buffer

is reached, then the GPTC signal is asserted.

Note that software can only set the CHx_CBUF_VAL bit to indicate to the hardware that the Next Address and

Transfer Count registers contain valid information. The CHx_CBUF_VAL bit can be cleared only by hardware.

Bit

Reserved

CH7_

CBUF_VAL

CH6_

CBUF_VAL

CH5_

CBUF_VAL

CH3_

CBUF_VAL

Reset

00000000

R/W

RSV

R/W!

Bit

Name

Function

–4

Reserved

This bit field should be written to 0 for normal system operation.

CH7_CBUF_

VAL

Chaining Buffer Valid for Channel 7

0 = The channel’s Next Address registers and Next Transfer Count registers are not valid.

Only hardware can clear this bit. Writing a 0 has no effect.

1 = Software sets this bit to indicate that the values of the channel’s Next Address registers

and Next Transfer Count registers are valid.

CH6_CBUF_

VAL

Chaining Buffer Valid for Channel 6

0 = The channel’s Next Address registers and Next Transfer Count registers are not valid.

Only hardware can clear this bit. Writing a 0 has no effect.

1 = Software sets this bit to indicate that the values of the channel’s Next Address registers

and Next Transfer Count registers are valid.

CH5_CBUF_

VAL

Chaining Buffer Valid for Channel 5

0 = The channel’s Next Address registers and Next Transfer Count registers are not valid.

Only hardware can clear this bit. Writing a 0 has no effect.

1 = Software sets this bit to indicate that the values of the channel’s Next Address registers

and Next Transfer Count registers are valid.

CH3_CBUF_

VAL

Chaining Buffer Valid for Channel 3

0 = The channel’s Next Address registers and Next Transfer Count registers are not valid.

Only hardware can clear this bit. Writing a 0 has no effect.

1 = Software sets this bit to indicate that the values of the channel’s Next Address registers

and Next Transfer Count registers are valid.

ELANSC520 Datasheet(PDF) 157 Page - Advanced Micro Devices

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