ELANSC520 datasheet(154/440 Pages) AMD

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GP DMA Controller Registers

11-22

Élan™SC520 Microcontroller Register Set Manual

Buffer Chaining Status (GPDMABCSTA)

Memory-Mapped

MMCR Offset D99h

This register provides the status of channels 3, 5, 6, and 7 when buffer chaining is enabled.

Bit Definitions

Bit

Reserved

CH7_EOB_

STA

CH6_EOB_

STA

CH5_EOB_

STA

CH3_EOB_

STA

Reset

00000000

R/W

RSV

R/W!

Bit

Name

Function

–4

Reserved

This bit field should be written to 0 for normal system operation.

CH7_EOB_

STA

End of Current Buffer in Channel 7

This bit is set by the GP bus DMA controller when the current buffer transfer is completed.

0 = The event has not occurred, or software cleared this bit by writing a 1.

1= The current buffer transfer is completed. In addition, an interrupt is generated if bit

CH7_INT_ENB is 1 in the GPDMABSINTENB register (see page 11-24).

Software should write a 1 to this bit (CH7_EOB_STA) to acknowledge the transfer completion

and clear the interrupt condition. This acknowledgment is usually done in the interrupt

handling routine if the interrupt is enabled.

Writing 0 to this bit has no effect. If this bit is 0, writing a 1 to it has no effect.

This bit’s value (when read) is meaningful only if buffer chaining is enabled.

CH6_EOB_

STA

End of Current Buffer in Channel 6

This bit is set by the GP bus DMA controller when the current buffer transfer is completed.

0 = The event has not occurred, or software cleared this bit by writing a 1.

1= The current buffer transfer is completed. In addition, an interrupt is generated if bit

CH6_INT_ENB is 1 in the GPDMABSINTENB register (see page 11-24).

Software should write a 1 to this bit (CH6_EOB_STA) to acknowledge the transfer completion

and clear the interrupt condition. This acknowledgment is usually done in the interrupt

handling routine if the interrupt is enabled.

Writing 0 to this bit has no effect. If this bit is 0, writing a 1 to it has no effect.

This bit’s value (when read) is meaningful only if buffer chaining is enabled.

CH5_EOB_

STA

End of Current Buffer in Channel 5

This bit is set by the GP bus DMA controller when the current buffer transfer is completed.

0 = The event has not occurred, or software cleared this bit by writing a 1.

1= The current buffer transfer is completed. In addition, an interrupt is generated if bit

CH5_INT_ENB is 1 in the GPDMABSINTENB register (see page 11-24).

Software should write a 1 to this bit (CH5_EOB_STA) to acknowledge the transfer completion

and clear the interrupt condition. This acknowledgment is usually done in the interrupt

handling routine if the interrupt is enabled.

Writing 0 to this bit has no effect. If this bit is 0, writing a 1 to it has no effect.

This bit’s value (when read) is meaningful only if buffer chaining is enabled.

ELANSC520 Datasheet(PDF) 154 Page - Advanced Micro Devices

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