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ELANSC520 Datasheet(PDF) 150 Page - Advanced Micro Devices

Part # ELANSC520
Description  Microcontroller
PDF  440 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 150 Page - Advanced Micro Devices

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GP DMA Controller Registers
11-18
Élan™SC520 Microcontroller Register Set Manual
GP-DMA Channel 5 Extended Transfer Count (GPDMAEXTTC5)
Memory-Mapped
MMCR Offset D91h
Register Description
This register provides the extended transfer count bits for Channel 5.
Bit Definitions
Programming Notes
Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4).
In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers.
Very large transfers could cause the PCI Host Bridge target controller to violate the 10-µs memory write maximum
completion time limit set in the
PCI Local Bus Specification, Revision 2.2.
7
6
5
4
3
2
1
0
Bit
DMA5TC[23
–16]
Reset
00000000
R/W
R/W!
Bit
Name
Function
7–0
DMA5TC
[23–16]
DMA Channel 5 Transfer Count Extension
This bit field provides the higher 8 bits of the transfer count for DMA Channel 5.
In enhanced mode, this bit field is used with the DMA5TC[15
–0] bit field in the GPDMA5TC
register (see page 11-81) to allow counts up to 16 M (16,777,216) transfers.
In normal mode, the value of this bit field (DMA5TC[23–16]) is ignored.



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