ELANSC520 datasheet(153/440 Pages) AMD

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GP DMA Controller Registers

Élan™SC520 Microcontroller Register Set Manual

11-21

Buffer Chaining Control (GPDMABCCTL)

Memory-Mapped

MMCR Offset D98h

This register controls the buffer chaining feature in enhanced mode.

Bit Definitions

Programming Notes

This register is ignored unless enhanced mode is enabled. Enhanced mode is enabled by setting the

ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4).

Bit

Reserved

CH7_

BCHN_ENB

CH6_

BCHN_ENB

CH5_

BCHN_ENB

CH3_

BCHN_ENB

Reset

00000000

R/W

RSV

R/W

Bit

Name

Function

–4

Reserved

This bit field should be written to 0 for normal system operation.

CH7_BCHN_

ENB

Buffer Chaining Enable for Channel 7

This bit enables buffer chaining via the Channel 7 Next Address and Channel 7 Next Transfer

Count registers. See the register descriptions beginning on page 11-32 and page 11-40.

When this bit is set, the CH7_CBUF_VAL bit in the in the GPDMABCVAL register becomes

effective (see page 11-25).

0 = Disable buffer chaining.

1 = Enable buffer chaining (enhanced mode only).

CH6_BCHN_

ENB

Buffer Chaining Enable for Channel 6

This bit enables buffer chaining via the Channel 6 Next Address and Channel 6 Next Transfer

Count registers. See the register descriptions beginning on page 11-30 and page 11-38.

When this bit is set, the CH6_CBUF_VAL bit in the in the GPDMABCVAL register becomes

effective (see page 11-25).

0 = Disable buffer chaining.

1 = Enable buffer chaining (enhanced mode only).

CH5_BCHN_

ENB

Buffer Chaining Enable for Channel 5

This bit enables buffer chaining via the Channel 5 Next Address and Channel 5 Next Transfer

Count registers. See the register descriptions beginning on page 11-28 and page 11-36.

When this bit is set, the CH5_CBUF_VAL bit in the in the GPDMABCVAL register becomes

effective (see page 11-25).

0 = Disable buffer chaining.

1 = Enable buffer chaining (enhanced mode only).

CH3_BCHN_

ENB

Buffer Chaining Enable for Channel 3

This bit enables buffer chaining via the Channel 3 Next Address and Channel 3 Next Transfer

Count registers. See the register descriptions beginning on page 11-26 and page 11-34.

When this bit is set, the CH3_CBUF_VAL bit in the in the GPDMABCVAL register becomes

effective (see page 11-25).

0 = Disable buffer chaining.

1 = Enable buffer chaining (enhanced mode only).

ELANSC520 Datasheet(PDF) 153 Page - Advanced Micro Devices

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