ELANSC520 datasheet(155/440 Pages) AMD

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GP DMA Controller Registers

Élan™SC520 Microcontroller Register Set Manual

11-23

Programming Notes

The interrupt output is shared between the four channels 3, 5, 6, and 7. If more than one interrupt is asserted and

software acknowledges one of the interrupts (by setting the corresponding CHx_EOB_STA bit), any other pending

interrupts remain asserted. Software has the option of acknowledging all pending CHx_EOB_STA bits and handling

all of the interrupts.

Buffer chaining is enabled separately for each channel in the GPDMABCCTL register (see page 11-21).

CH3_EOB_

STA

End of Current Buffer in Channel 3

This bit is set by the GP bus DMA controller when the current buffer transfer is completed.

0 = The event has not occurred, or software cleared this bit by writing a 1.

1= The current buffer transfer is completed. In addition, an interrupt is generated if bit

CH3_INT_ENB is 1 in the GPDMABSINTENB register (see page 11-24).

Software should write a 1 to this bit (CH3_EOB_STA) to acknowledge the transfer completion

and clear the interrupt condition. This acknowledgment is usually done in the interrupt

handling routine if the interrupt is enabled.

Writing 0 to this bit has no effect. If this bit is 0, writing a 1 to it has no effect.

This bit’s value (when read) is meaningful only if buffer chaining is enabled.

Bit

Name

Function

ELANSC520 Datasheet(PDF) 155 Page - Advanced Micro Devices