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GP DMA Controller Registers

Élan™SC520 Microcontroller Register Set Manual

11-43

Slave DMA Channel 0 Transfer Count (GPDMA0TC)

Direct-Mapped

I/O Address 0001h

This register contains bits 15–0 of the transfer count for Channel 0 during DMA operation.

Bit Definitions

Programming Notes

To ensure that the lower byte of this register (GPDMA0TC) is always accessed first, software should precede any

access to this register with a write to the SLDMACBP register (see page 11-57) to clear the slave DMA byte pointer.

In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers.

Very large transfers could cause the PCI Host Bridge target controller to violate the 10-µs memory write maximum

completion time limit set in the

PCI Local Bus Specification, Revision 2.2.

Bit

DMA0TC[15

–0]

Reset

xxxxxxxx

R/W

R/W!

Bit

Name

Function

7–0

DMA0TC

[15–0]

DMA Channel 0 Transfer Count (16-Bit Register)

This 8-bit field is used in two successive I/O accesses to read or write the channel’s transfer

count bits 15–0.

Bits 7–0 of the channel’s transfer count can be read from or written to this bit field immediately

after a write to the SLDMACBP register (see page 11-57).

Bits 15–8 of the channel’s transfer count can be read from or written to this bit field

immediately after transfer count bits 7–0 are read from or written to this bit field.

The actual number of transfers is one more than the programmed transfer count value.

ELANSC520 Datasheet(PDF) 175 Page - Advanced Micro Devices