DP8496 datasheet(25/92 Pages) NSC

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40 Functional Description (Continued)

This command may be used for many special applications

such as

1 Writing data fields that are split by servo information

2 Writing to non-hard sectored Header Segments

3 Headerless sectoring

This command could be useful when used with the LOI

(Load On Index) bit in the Timer Prescaler register Write

Unformatted can be ‘‘dropped’’ accurately on the track us-

ing the time from Index as a count

Read Unformatted

This command will read a Data Segment only (although the

Data Segment registers may be programmed to appear as a

Header Segment) No header fields will be read counted

through or written After the specified starting condition a

Data Synch will be searched for After Data Synch is found

the data field will be read and transferred to buffer memory

Data CRCECC will be optionally checked

This command could be useful when used with the LOI

(Load On Index) bit in the Timer Prescale register Read

Unformatted can be ‘‘dropped’’ accurately on the track us-

ing the time from Index as a count It is also useful for read-

ing split data fields due to embedded servo

Start Correction Cycle

This command will start the internal ECC correction cycle

When the correction cycle has completed A Disk Comple-

tion Interrupt will be generated If the correction cycle was

successful no error will be indicated If unsuccessful a Disk

Complete Interrupt will occur with an error indication The

Disk Status register will report the Correction Failed condi-

tion This operation like all other operations may be started

any time another disk operation is not in progress Refer to

Section 434 for a discussion of the procedure for correct-

ing the data

Disk Control (DCTL)

11h

7654

HSS

WPSIG

WGF

PLL

RES

IR Interlock Required

The Interlock register (Header Byte Counter register)

must be written to after the Disk Data Controller has

completed a header operation and before the begin-

ning of the Data Postamble field If the Interlock register

is not written to in time the command will terminate

with the LI (Late Interlock) bit in the Disk Status register

set to ‘‘1’’ This allows the safe updating of header for-

matting registers during a Format operation Normally

used with the HNC (Header Complete or Next Com-

mand) bit in the Disk Interrupt Enable register set to ‘‘1’’

to enable Header Complete interrupts See Section

434 for a description of this technique

Normal operation No interlock function

IS IndexSectorAMF Interrupt

This bit controls the generation of an interrupt at each index

sector or AMF This interrupt may be masked by the IS

(IndexSector) bit in the Disk Interrupt Enable register

An interrupt will be generated as determined by Table

417 In general this will generate an interrupt at each

Index pulse for soft sectored drives each Index or AMF

signal for pseudo-hard sectored drives or at each In-

dex or Sector pulse for hard sectored drives

An interrupt will be generated by each Index pulse

HSS Hard or Soft Sectored

Works in conjunction with the DT (Drive Type) bit to control

the AME and the AMFSector pins In general this bit

should be set for hard or pseudo-hard sectored drives and

cleared for soft sectored drives Refer to Table 417 for the

specific use of this bit

DT Drive Type

Works in conjunction with the HSS (HardSoft Sectored) bit

to control the AME and the AMFSector pins In general

this bit should be set for pseudo-hard sectored drives Refer

to Table 417 for the specific use of this bit

WPSIG Write Post SectorIndex Gap

This bit is only used in Write Header or Format operations

WGATE is asserted during the Post SectorIndex Gap

when a header is written

WGATE is not asserted during the Post SectorIndex

Gap

WGF Write Gate Format

This bit will allow a single revolution format operation with

an RLL code In some applications if WGATE pulses low for

2 bit times an external ENDEC will generate a valid pream-

ble pattern This bit will only effect the operation of WGATE

during the Data Gap field

WGATE is deasserted for 2 bit times at the beginning of

the Data Gap field of each sector written

WGATE remains asserted throughout the Data Gap

field

PLL PLL Recovery Time

This bit is only used in soft sectored mode It is used to

control the amount of PLL relock time given to an external

synchronizer When used with the National’s DP8459 or

DP8469 the two byte choice gives the shortest necessary

preamble lengths and takes advantage of the zero phase

start of these PLLs When using other PLLs the six byte

choice should be used See Section 434

RGATE is deasserted for six byte times following a

synch mis-compare in Soft Sector mode

RGATE is deasserted for two byte times following a

synch mis-compare in Soft Sector mode

RES Reset

Reset Active Setting this bit initiates a Disk Data Con-

troller reset operation Any disk command which may

be in progress will be terminated after transferring up to

four additional bytes See Table 31 for a summary of

registers affected by this reset

This bit will also be set by asserting the CRST pin

Once this bit is set (even by CRST) the only method to

clear it is by writing a zero to this bit

Normal Operation Clearing this bit terminates the reset

condition The processor must wait a minimum of 17

RCLK cycles after reset has begun before clearing re-

set

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