DP8496 datasheet(17/92 Pages) NSC

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40 Functional Description (Continued)

Ready Pin

The RDY pin may be connected to the processor’s memory

access control pin (or ‘‘wait state’’ pin) After WR or RD

goes low the processor will be ‘‘wait-stated’’ until the data

from buffer memory becomes available This is the easiest

method of access to buffer memory since the job of regulat-

ing the speed of the processor access is done entirely in

hardware by the DP84967 The only requirement is that the

processor used with the DP84967 have some type of asyn-

chronous access line

When the processor reads the Buffer Memory Data register

the RDY pin will become deasserted if the data is not yet

available It will become asserted when the data is valid For

a write operation the RDY pin will become deasserted if a

previous write has not yet been transferred to buffer memo-

To enable this mode the BMD (Buffer Memory Data) bit in

the Disk Interrupt Enable register must be set to zero The

RDY pin will be always deasserted while in the ZilogMoto-

rola mode

If non-contiguous address locations are to be accessed the

processor must poll the ER (ErrorReady) bit in the Disk

Interrupt register for a ‘‘1’’ before the Processor Pointer reg-

isters may be modified

Software Polling

If no asynchronous access pin is available or you choose

not to use it software polling may be used With the BMD

(Buffer Memory Data) bit in the Disk Interrupt Enable regis-

ter set to ‘‘0’’ not only is the Ready pin enabled but the

RE (ReadyError) bit in the Disk Interrupt register will oper-

ate as ‘‘Buffer Memory Data Ready’’ and may be polled A

‘‘1’’ in the ER bit indicates that the Buffer Memory Data

that it is not ready

A ‘‘1’’ in the ER bit also indicates that the Processor Point-

er registers may be modified by the Processor

Disk Interrupt

12h

76543210

GCI

SCI

HNC

CCI

Interrupt Error

By setting the BMD (Buffer Memory Data) bit in the Disk

Interrupt Enable register to a ‘‘1’’ the RDY pin is disabled

Also the ER bit in Disk Interrupt register will operate as a

true interrupt This ‘‘Error’’ interrupt indicates that the Buffer

Memory Data register has been accessed before the data is

valid The processor should simply wait a certain amount of

time between each access to the Buffer Memory register If

an interrupt occurs simply clear the interrupt wait an addi-

tional amount of time and try the access again

Interrupt after Indicates that the previous write has not yet

a write

been transferred to the buffer memory The

previous data is still retained and the DMA

process is unaffected by the new write The

data just written will be ignored

Interrupt after Indicates that the Buffer Memory Data regis-

a Read

ter has not yet been bloaded with the data

requested The data just read is invalid

TABLE 49 RDY Pin and Interrupt Summary

BMD Bit in Disk

Function of ER Bit in

Interrupt Enable

RDY Pin

Disk Interrupt Register

Disabled

Buffer Memory Error

Enabled

Buffer Memory Ready

If non-contiguous address locations are to be accessed the

processor must verify that the Processor Pointer registers

can be modified To do this the BMD bit in the Disk Interrupt

Enable register must be set to ‘‘0’’ This enables the soft-

ware polling mode While in this mode the Processor must

poll the ER bit in the Disk Interrupt register When this bit is

‘‘1’’ the Processor Pointer registers may be modified The

Interrupt Error mode may then be re-enabled by setting the

BMD bit in the Disk Interrupt Enable register back to ‘‘1’’

429 Parity

Buffer memory parity is generated when writing to buffer

memory and verified while reading from buffer memory only

if enabled by the BPE (Buffer Parity Enable) bit in the Setup

2 register

In general parity (if enabled) is always checked at the point

where the data exits the chip Therefore parity errors gener-

ated within the DP84967 are checked as well as external

parity errors

When the processor accesses data from buffer memory

parity information cannot be determined through the Buffer

Memory Data register If the Setup 2 register is configured

to check buffer memory parity a parity error detected while

reading the Buffer Memory Data register will be reported in

the SCSI Operation register (43h) The SCSI Operation reg-

ister may be polled after a block of data has been read from

the Buffer Memory Data register Once a parity error is de-

tected it is cleared only by reading the SCSI Operation reg-

ister

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