DP8496 datasheet(56/92 Pages) NSC

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40 Functional Description (Continued)

I Identify Message

Since this register is used only for the Identify Message this

bit must always be set to ‘‘1’’ If it is not set to ‘‘1’’ no new

command can be executed

This bit will always be a ‘‘1’’ when read following a success-

ful ‘‘Wait for Select’’ operation which included a Message

Out phase Otherwise an ‘‘Uncompleted Command’’ inter-

rupt would be generated

DISC Disconnect Privilege

When this register is used for the Message In phase during

a Reselect combination command this bit has no meaning

Following a ‘‘Wait for Select’’ command which included a

Message Out phase this bit indicates the ability of the Initia-

tor to support disconnection and reconnection A ‘‘1’’ indi-

cates this support A ‘‘0’’ indicates no support

TAR Logical Unit Target

When this register is used for the Message In phase during

a Reselect combination command this bit has no meaning

Following a ‘‘Wait for Select’’ command which included a

Message Out phase this bit specifies where the Identify

Message is directed to A ‘‘0’’ indicates a logical unit (see

the LUN field) A ‘‘1’’ indicates a target routine See the

SCSI-2 specification

Reserved

Since these bits are reserved it is recommended that these

bits be set to ‘‘0’’ before a Reselect combination command

is issued

These bits will always be a ‘‘0’’ when read following a suc-

cessful ‘‘Wait for Select’’ operation which included a Mes-

sage Out phase Otherwise an ‘‘Uncompleted Command’’

interrupt would be generated

LUN Logical Unit Number

Before a Reselect combination operation this field should

be set with the Logical Unit Number from which the data is

being read from or being written to

Following a ‘‘Wait for Select’’ command which included a

Message Out phase this field indicates the Logical Unit

Number associated with the command to follow They

should match the LUN bits contained in the Command De-

scriptor Block

Destination ID (DID)

46h

76543210

Phase Code

MCH

Destination ID

Phase Code

These four bits set up the SCSI bus phase for which the

DP84967 will match or not match to generate the Phase

Compare interrupt Comparison is qualified with the active

edge of the REQ signal in both match and mismatch cases

The Phase Code bit patterns are exactly the same as the

Status Code patterns defined in Table 425 in the SCSI

Status register

MCH Match

Looks for a match with the indicated Phase Code If

found a ‘‘Phase Compare’’ interrupt will be generated

Looks for a mismatch of the current SCSI bus phase

with the indicated Phase Code This code should be

loaded after the Target’s phase is stable (REQ is as-

serted) if the DP84967 is in Initiator mode If the phase

changes a ‘‘Phase Compare’’ interrupt will be generat-

Destination ID

This ID is OR’ed with SCSI ID from the Setup 2 register This

OR’ed value is asserted on the SCSI bus during Selection or

Reselection phases Parity is also generated

Source ID (SID)

47h

R Only

76543210

VID

Source ID

While in Target mode during the Selection Phase or while in

Initiator mode during the Reselection Phase the Initiator’s

ID and the Target ID are both present on the SCSI bus Our

Target ID (SCSI ID in Setup 2 register) is masked off and

the resulting Initiator ID can be read from Source ID field

The VID (Valid ID) bit will be ‘‘1’’

If there is no Initiator ID on the SCSI bus during Selection

the VID bit will be ‘‘0’’ If the DP84967 is not properly Se-

lected (ex three or more bits set) the DP84967 will not

respond and the VID bit will be ‘‘0’’

SCSI Status (SSTAT)

48h

R Only

76543210

DBR

BMR

Error Code

Status Code

DBR Data Buffer Ready

In Manual mode with the HE (Handshake Enable) bit set to

‘‘1’’ DBR is used to indicate when to send or receive the

next byte

The SCSI Data register is full If receiving the SCSI

Data register should be read If transmitting the proces-

sor should wait until DBR e 0

The SCSI Data register is empty If receiving the proc-

essor should wait for another byte to arrive If transmit-

ting the SCSI Data register should be written

The DBR bit is reset whenever an error is cleared in the

SCSI Interrupt register An error is defined as a Completion

Interrupt Code value between 2h and 7h in the SCSI Inter-

rupt register

BME Buffer Memory Parity Error

A parity error was detected while writing data to the SCSI

port from buffer memory This indicates a parity error in buff-

er memory This will terminate any SCSI command at the

end of the current transfer phase

The ‘‘Buffer Memory Parity Error’’ completion interrupt will

be generated

This bit is cleared to zero when a new command is down-

loaded and executed

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