DP8496 datasheet(65/92 Pages) NSC

65 / 92 page

50 Application Information Buffer Memory Interfacing

in a Fast SCSI Implementation

Today’s hard disk systems require high throughput in each

stage from the magnetic media to the CPU Additionally

users wish to have wide access to a great many different

drive types and manufacturers This was the motivation for

the SCSI interface To achieve high throughput SCSI-2 de-

fines a differential cable transmission scheme and a Fast

option that allows transfers at 10 MBytessec At the same

time faster serial data rate from the disk drive is required in

order to utilize this increased bus bandwidth Thus disk data

rates of 33 Mbitssec (or 42 MBytessec) are becoming

common Into this fray of information exchange is the added

requirements of error correction and drive control hence

the need for a processor to also have access to the data

This example application shown in

Figure 51 illustrates

how the DP8497 can be used to implement a drive design

that achieves 10 MBytessec SCSI transfer rate and a

33 Mbitsec disk data rate while using only low-cost 100 ns

variety DRAMs The key feature of the DP8497 that makes

this possible is its word-wide buffer memory port This ex-

ample application requires the buffer memory port to pro-

vide enough bandwidth to support 10 MBytessec (SCSI) a

42 MBytessec (Disk) a Processor Accesses a DRAM

Refreshes under the maximum load The DP84967 auto-

matically handles refresh if DRAMs are used The refresh

occurs once every 128 BCLK cycles and takes 5 BCLK cy-

cles to complete Hence a refresh cycle starts after 123

BCLK cycles Under the maximum load the FIFOs will

transfer 4 words in 9 BLCK cycles This gives over 13 trans-

fers per refresh Using a word length of 2 bytes this means

that 2 c 13 c 4 or 104 bytes will be transferred in 123

BLCK cycles If BCLK is running at 20 MHz then there is at

least 1691 MBytessec available for disk SCSI and proces-

sor accesses With the above constraints this allows the

processor to have access to a bandwidth of 27 MBytessec

under the worst case

Standard 100 ns fast page mode DRAMs have a cycle time

of 180 ns for a random access Page mode DRAMs the

most common type allow a faster access to data that

shares the same ‘‘page’’ as the previous access Each of

these ‘‘same page’’ accesses takes 55 ns Thus with a burst

of 4 words under a high load condition there is one random

access (usually) followed by 3 fast accesses to the same

page The minimum time in which these accesses could be

achieved would be 180 ns a 3 c 55 ns or 345 ns The time

for a burst read of 4 words is 9 BCLKs thus at a BCLK of

20 MHz the total time taken is 450 ns This is more than

enough time for the DRAM With this ability it is possible to

have a sustained memory bandwidth of 169 MBytessec

with 100 ns Page mode DRAMs However the random and

page access times cycle time and setup and hold times

should be checked against the buffer memory timing spec

for the particular type of DRAMs used

Since page mode DRAMs have a limited page size there is

often a need to change pages This action requires a new

row address to be presented to the DRAMs If a burst will

require the address to change its page then the burst is

truncated to fit up to the end of the page and a new burst

transfer occurs at the beginning of the page boundary The

worst case is when there is only one word that can be trans-

ferred at the end of the page Thus when the burst should

have transferred 4 words in 9 BCLK cycles that same four

word transfer now takes 5 (1 word) a 8 (three words) or 13

BCLK cycles The system will only cross a page boundary at

the most once every page size In the DP84967 this is 256

addresses If transfers are never aligned to page bounda-

ries the following sequence of events will occur for a 256

word transfer

3 blocks of 54 words each terminated with a refresh

1 block of 54 words terminated with a refresh and a

page boundary

1 block of 40 words to complete the 256 word

transfer

Total of 256 words transferred

This requires the following number of corresponding cycles

3 blocks of 128 BCLK cycles

1 block of 132 cycles because of the page boundary

1 block of 90 cycles for the remaining 40 words

Total of 606 BCLK cycles taken

Therefore the corresponding transfer rate becomes 16898

MBytessec Note that the reduction in bandwidth due to

page effects is only 07%

Figure 53 illustrates the net at-

tainable bandwidth as a function of BCLK frequency

The 512 KByte buffer memory shown in the schematic

makes possible large cache buffers for the purpose of re-

ducing effective access times The 256k c 18 DRAM chip

was chosen to minimize the number of chips while still

maintaining the word-wide bandwidth In this way only one

DRAM chip is used However cheaper x4 DRAM chips may

be used at the cost of increased board space

The

DP84967s support other widths of DRAMs such as 256k x

4s and 1 Meg x 1s The SDDC can support the load of up to

12 DRAMs The example also uses parity to help ensure

that the data from the host computer is not errantly changed

on its way to the magnetic media or visa versa

The Rest of the Circuit

To start the connection between the SCSI cable and the

differential transceivers requires termination The termina-

tion resistors are not shown in the schematic however they

should be the same as defined in the SCSI standard This is

shown in

Figure 52

The DB8497 has the differential transceiver enable controls

on chip These connect directly to the drive enable pins on

the DS36954As In this way complete differential SCSI can

be achieved by only adding the transceiver chips and termi-

nation resistors

The mController used is the HPC46003 This 16-bit proces-

sor is capable of achieving high instruction rates and uses a

very compact coding scheme Other versions of the mCon-

troller have internal ROM that may be mask programmed

All versions have at least 256 bytes of internal RAM

This circuit has an external 32 KBytes of ROM for prototyp-

ing An additional 32 KBytes of RAM is provided to allow the

HPC to download programs through its UART again for pro-

totyping and also for additional storage Since the mCon-

troller has been forced into 8-bit access only a single latch

is required to hold the address for the RAM and ROM

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