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DP8496 Datasheet(PDF) 77 Page - National Semiconductor (TI) |
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DP8496 Datasheet(HTML) 77 Page - National Semiconductor (TI) |
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77 / 92 page  70 AC Specifications (Continued) 712 BUFFER MEMORY DYNAMIC RAM REFRESH TLF11212 – 46 ID Symbol Parameter Formula BCLK e 20 MHz Units Min Max Min Max 121 crasa BCLK to RAS Asserted (See 111) 30 ns 122 crasd BCLK to RAS and CAS Deasserted (112) 30 ns 123 rcr ReadWrite Cycle Time for Refresh bcp a bcl 72 ns 124 rasr RAS Pulse Width for Refresh 2 bcp a bch b 5 117 ns 125 rpr RAS Precharge Time for Refresh 2 bcp a bcl b 5 117 ns 126 csr CAS to RAS Setup Time bcp b 5 bcp a 545 55 ns 127 chr CAS Hold Time 2 bcp a bch b 5 117 ns 128 cpn CAS Precharge Time bcp a bcl b 567 ns 129 rpc RAS to CAS Precharge Time bcp a bcl b 567 ns Note 1 bcp means Bus Clock Period being used bch and bcl refer to the positive and negative pulse widths of Bus Clock in use Note 2 RAS may be asserted on either edge of BCLK 713 DISK READ DATA AND READ GATE TIMING TLF11212 – 47 ID Symbol Parameter DP84967-33 DP84967-50 Max Units Min Min 131 rds Read Data Setup to RCLK 7 5 ns 132 rdh Read Data Hold from RCLK 10 9 ns 133 is Index Setup to RCLK 10 10 ns 134 ih Index Hold from RCLK 10 10 ns 135 crg RCLK to Read Gate 15 ns 77 |
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