DP8496 datasheet(16/92 Pages) NSC

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40 Functional Description (Continued)

426 Processor Access to Buffer Memory

The processor gains access to the buffer memory by load-

ing the Processor Pointer 0 – 2 registers with the address of

the byte in buffer memory that needs to be accessed The

Processor Pointer 0 register should be loaded last The data

is then read from or written to the Buffer Memory Data regis-

ter

The Buffer Memory Data register can be read or written to

just like any other register on the DP84967 The same AC

specifications apply to this register However the data read

from the Buffer Memory Data register may not be valid im-

mediately and the data written to the Buffer Memory Data

diately

The Buffer Memory Data register is simply another DMA

channel trying to access the buffer memory Since the arbi-

tration priority of the Processor Interface is not the highest

there may be a delay before the contents of the Buffer

Memory Data register are actually transferred to or from the

buffer memory The amount of the delay depends on how

much extra bandwidth was allowed by the system designer

in the buffer memory data path

The Processor Pointer registers should be loaded by the

processor from most-significant byte to least-significant

byte Immediately after the Processor Pointer 0 register is

written to the DP84967 will initiate an arbitration for a read

from buffer memory at the location pointed to by the Proc-

essor Pointer registers Once granted the buffer memory

location is read and the value is placed in the Buffer Memo-

ry Data register

In the case of a write operation the Buffer Memory Data

Processor Pointer 0 register If the processor writes to the

buffer memory data register before the DP84967 com-

pletes a buffer memory read no buffer memory read will

occur

To determine when the transfer has completed one of the

three techniques described in Section 428 must be used

Same techniques should be used if sequential reads or

writes are issued

427 16-Bit Wide Access

If the 16-bit buffer memory mode is enabled in the Setup 1

change The processor should load the Processor Pointer

registers from most-significant byte to the least-significant

byte Immediately after the Processor Pointer 0 register is

written to the DP84967 will initiate an arbitration for a read

from buffer memory at the location pointed to by the Proc-

essor Pointer registers

This will result in the entire 16-bit word being read from

buffer memory However the Buffer Memory Data register

will only allow access to the 8 bits that were requested

based on the least significant bit in the Processor Pointer 0

can be accessed by the processor By using an even proc-

essor pointer address and setting AI (Auto Increment) to

‘‘1’’ the low byte and high bytes of each word will be ac-

cessed in order

Byte wide data written to the Buffer Memory Data register

by the processor replaces the low byte or high byte depend-

ing on the least significant bit in the Processor Pointer 0

the addressed word location the 16-bit word is written back

to buffer memory This ensures that only one byte is effect-

ed with each write

If the AI (Auto Increment) mode is enabled in the Setup 2

each read of the Buffer Memory Data register by the proces-

sor or after each transfer from the Buffer Memory Data reg-

ister to the buffer memory To complete a 16-bit processor

read the processor must read the Buffer Memory Data reg-

ister again When writing the processor must write to the

Buffer Memory Data register again to change the other byte

of the memory word After this second byte is altered the

16-bit word is again written back to buffer memory This

sequence completes a processor modification of a 16-bit

buffer memory location

If Auto Increment mode is enabled and the processor writes

to the Buffer Memory Data register twiceloading the low

byte and the high byte

before the DP84967 initiates a

buffer memory read no buffer memory read will occur This

new 16-bit value will then be written to buffer memory twice

The data is transferred twice to buffer memory to increment

the processor pointer to the next word

428 Sequential Accesses of Buffer Memory

To make sequential reads and writes by the processor more

convenient the Processor Pointer registers may be pro-

grammed to automatically increment after each access to

the Buffer Memory Data register The AI (Auto Increment)

bit in the Setup 2 register determines whether the Processor

Pointer will automatically increment The Processor Pointer

will increment after each read or write of the Buffer Memory

Data register then the DP84967 will read the next RAM

location from buffer memory Sequential writes are accom-

plished in the same way Mixed reads and writes are also

allowed

There are three methods to insure safe transfer of data

tofrom buffer memory by the processor Using the RDY

pin software polling or using the Interrupt Error

The method chosen will largely be based upon the proces-

sor facilities available If the processor has a Ready DTACK

or some other asynchronous access control pin the RDY

output pin of the DP84967 can be used to automatically

control access to Buffer Memory Data register If a proces-

sor is chosen without such a facility the software polling

operation is the next best choice

The Disk Interrupt Enable register is used to select between

the different processor access techniques Only bit 6 of this

ter will be described in the Disk Data Controller description

in Section 432 A summary of the RDY pin function and the

buffer memory interrupt function is shown in Table 49

Disk Interrupt Enable

13h

76543210

BMD

GCI

SCI

HNC

CCI

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