DP8496 datasheet(53/92 Pages) NSC

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40 Functional Description (Continued)

SCSI Data (SDAT)

41h

76543210

Data

This register allows access to the SCSI Data Bus by the

processor while in Manual Mode See Section 443 for de-

tails about Manual Mode data transfers These bits are as-

serted only if a ‘‘1’’ is written On the single-ended SCSI bus

that is open-drain writing a ‘‘0’’ turns off the driver and al-

lows the bus to float

This register should only be used while in the Manual Mode

There are two exceptions

1 Just before switching from Automatic to Manual Mode

See Section 443

2 Just before a Transfer Pad command See the Transfer

Pad command description

SCSI Control (SCTL)

42h

76543210

BSY

SEL

ATN

MSG

REQ

ACK

The SCSI Control register is really an image of eight out of

the nine SCSI control lines The direction and RW attri-

butes of these bits are determined by the Target or Initiator

mode and whether in Automatic or Manual operation A

summary of bit attributes are given in Table 422 When they

are read ATN CD IO and MSG bits reflect the logical

OR of what is on the SCSI bus and what the chip is attempt-

ing to drive These two values may not be the same under

some abnormal conditions For example on the DP8497

incorrect use of the Differential SCSI register in manual

mode or an external circuit fault may cause such a conflict

The SCSI RST signal does not appear in this register but is

driven by the DP84967 from the SCSI Operation register

When RST is driven by another SCSI device it will generate

a ‘‘SCSI Reset’’ interrupt

Note the ATN line is writable in Automatic mode when con-

figured as an Initiator However the SWA (Select With At-

tention) bit in the SCSI Operation register should be used to

assert the ATN signal properly during the Selection phase

The ATN bit is only intended to be written during the Trans-

fer Info or Transfer Pad commands

These bits are asserted only if a ‘‘1’’ is written Since the

SCSI bus is open-drain writing a ‘‘0’’ turns off the driver and

allows the bus to float

TABLE 422 Bit Attributes in SCSI Control Register

Sig

Target

Initiator

Dir

Auto

Man

Dir

Auto

Man

BSY

SEL

ATN

MSG

REQ

ACK

SCSI Operation (SOP)

43h

76543210

SWA

APE

PEP

RST

This register must be loaded before SCSI Block Count and

SCSI Block Size registers

TI TargetInitiator

This bit must not be changed while an information transfer

phase is in progress It can be changed after an unexpected

Selection or Reselection but in these cases it must be

changed before a transfer command is issued It also can

be changed while the SCSI bus is idle

Caution

If the last command written to the SCSI Command

a Clear Pending Command should be issued before the (TI

bit is modified Even if the last command has completed and

the interrupt has been processed the Clear Pending Com-

mand should be issued If this is not done an ‘‘Invalid Com-

mand’’ interrupt will be generated after the TI bit is

changed

Target Mode All commands and modes relevant to the

Target functions are enabled ((Re)Select command

becomes Reselect)

Initiator Mode All commands and modes relevant to

the Initiator function are enabled ((Re)Select command

becomes Select)

SWA Select With Attention

When in the Initiator mode and Selecting the ATN sig-

nal will be asserted as per SCSI specifications

When in the Initiator mode and Selecting the ATN line

will not be asserted

When executing Transfer InfoPad commands ATN can be

controlled through the SCSI Control register In addition

when executing Transfer InfoPad commands while execut-

ing any Information In phase ATN will be asserted on a

SCSI bus parity error if enabled in the Setup 2 register

AM AutomaticManual Mode

Enables the Automatic mode of operation enabling the

SCSI sequencer SCSI commands may be issued to the

SCSI Command register The chip will respond properly

to (Re)Selections

Manual Mode completely disables the SCSI sequencer

and clears any curent SCSI command No SCSI com-

mands may be issued in this mode but it has no effect

on the Disk Data Controller In this mode the processor

has complete control over the SCSI bus and any se-

quence legal or illegal can be performed

Automatic to Manual Restrictions

Before switching from

Automatic mode to Manual mode the TI (TargetInitiator)

bit in this same register should be set to the desired value

Also the HE (Handshake Enable) bit in the Synchronous

Transfer register should be programmed If the DP84967 is

not currently connected to the SCSI bus the HE bit should

be set to ‘‘0’’ This guarantees that all 18 SCSI signals will

remain glitchless during the AM bit transition If the HE bit

is set to ‘‘1’’ only the 9 SCSI Bus Control signals are guar-

anteed to remain glitchless

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