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DP8496 Datasheet(PDF) 37 Page - National Semiconductor (TI) |
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DP8496 Datasheet(HTML) 37 Page - National Semiconductor (TI) |
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37 / 92 page  40 Functional Description (Continued) TLF11212 – 15 FIGURE 48 RGATE Operation during Search for Synch RGATE Timing for Soft Sectors Ideally RGATE should transition from deasserted to assert- ed only while the drive’s head is positioned over a preamble field Proper programming of the gap lengths in the Format registers strive for this condition However for soft sectored drives it is impossible to avoid asserting RGATE over non-preamble fields as shown in Fig- ure 49 For soft sectored drives the DP84967 employs a RGATE algorithm to allow an external PLL to re-lock to the proper frequency while searching for a preamble and address mark This algorithm is shown in Figure 48 While reading a preamble (or what the DP84967 thinks is a preamble) the first non-zero bit clears a bit counter If the data read for this bit and the next 7 bits do not match the proper Synch regis- ter RGATE is deasserted If a Synch match is made the read operation continues to its conclusion If RGATE is deasserted it will remain deasserted for either two or six byte times This time is determined by the PLL (PLL Recovery Time) bit in the Disk Control register 37 |
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