DP8496 datasheet(29/92 Pages) NSC

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40 Functional Description (Continued)

TABLE 413 ECC Byte Ordering

CRCECC

Syndrom Bytes

(Most Significant to Least Significant)

When Read

Selected

(Individual Bits Are in Reverse Order)

Most Significant Byte

Least Significant Byte

Correction Cycle

16-Bit

ESR6

ESR0

32-Bit

ESR6

ESR5

ESR1

ESR0

48-Bit

ESR6

ESR5

ESR4

ESR2

ESR1

ESR0

56-Bit

ESR6

ESR5

ESR4

ESR3

ESR2

ESR1

ESR0

Correction Mask

(Read in Order)

(Individual Bits Are in Correct Order)

1st

2nd

3rd

4th

5th

Correction Cycle

After Successful

32-Bit

ESR1

ESR5

ESR6

48-Bit

ESR1

ESR2

ESR4

ESR5

56-Bit

ESR1

ESR2

ESR3

ESR4

ESR5

Note

ESRx e ECC Shift Register x

ECC Shift Register (ESRx)

00–06h

R Only

76543210

Pattern

The shift register will yield different types of information de-

pending on when it is read If read after a successful disk

data read or write operation they contain zeros

Reading the shift register after an CRCECC error produces

the syndrome bytes for that particular error This syndrome

may be stored and compared with syndromes from multiple

reads to verify a hard error condition

An error correction command may be issued to attempt to

correct the data read from the disk When the ECC Shift

tains a correction mask which can be used to correct the

error contained in Buffer Memory See Section 43 for a

discussion of the procedure for error correction

ECC Byte CountLow (ECCL)

18h

R Only

76543210

Byte Count (Low)

ECC Byte CountHigh (ECCH)

19h

R Only

76543210

Byte Count (High)

These two registers contain an offset byte count after a

correction cycle which when added to the address of the

start of the offending sector identifies the location of the

error These registers only contain valid information after

the end of a correction cycle

433 Format Registers

The disk format is defined by using the format pattern and

control registers Generally these registers are set up in

pairs a pattern register and a control register In each pair

the pattern register is loaded with an appropriate 8-bit pat-

tern that will be written to the disk during a Format or Write

operation or will be used during a Read or Compare opera-

tion for byte alignment or a comparison in locating a sector

The control register will generally determine how many

times the pattern is repeated or the count Refer to Table

414 and Table 415 to relate each pattern and control regis-

ter to the actual disk format

These registers should be loaded during the initialization

process for the particular format chosen Reset does not

effect these registers

Be sure to observe the restrictions on count fields being set

to zero as specified in the individual register descriptions

There are some count fields which may not be zero All

fields listed in Table 414 and 415 are programmable

RGATE and WGATE are asserted during certain fields This

is shown in

Figure 49 and Figure 410 at the end of the

section on Disk Operations (434)

Post SectorIndex Count (PSIG) 20h

76543210

Count

Sets the number of bytes in the Post SectorIndex field The

pattern used is from the Gap 3 Pattern register WGATE will

be asserted during this field according to the WPSIG (Write

Post SectorIndex Gap) bit in the Disk Control register This

field can be used to skip sectored or wedge servo fields

RGATE is never asserted during this field for hard and pseu-

do-hard sectored drives The Post SectorIndex field is not

used if the DCOZ (Drive Command On Zero) bit is set in the

Timer Prescale register)

For soft-sectored drives PSIG is only used before the first

sector For other sectors PSIG is assumed to have a length

of one Range is 1 – FF

Header Preamble Count (HPC)

21h

76543210

Header Gap

Header Preamble

Header Gap

Sets the number of bytes in the Header Gap field The pat-

tern used is from the Preamble Pattern register Used to

separate the time between RGATE and WGATE assertions

WGATE is always asserted during this field for a write oper-

ation RGATE is never asserted during this field for hard and

pseudo-hard sectored drives Range is 1 – 7

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