DP8496 datasheet(70/92 Pages) NSC

70 / 92 page

70 AC Specifications

Refer to Section 80 for AC Timing Test Conditions

The timing values and formulae specified in this preliminary document are based on the chip’s design values and therefore are

intended to assist the user in making initial design choices Final AC Specifications will be determined after a thorough charac-

terization of the product has been performend

71 CLOCK TIMING

TLF11212 – 35

Symbol

Parameter

DP84967-33

DP84967-50

Max

Units

Min

bcl

BCLK Low (Note 1)

bch

BCLK High (Note 1)

bcp

BCLK Period (Note 1)

100

rcl

RCLK Low

600

rch

RCLK High

600

rcp

RCLK Period

1000

Note 1

BCLK frequency should not be less than 10 MHz to ensure proper DRAM refresh and to guarantee proper SCSI bus timing Please refer to Table 421A for

Synchronous Information Transfers

Note 2

BCLK can be as low as 2 MHz to save power while the chip is idle however the DRAM contents will be invalid

72 REGISTER READ

(NSCIntel Mode)

TLF11212 – 36

Symbol

Parameter

Min

Max

Units

aswi

Address Strobe Width

asdv

Address Strobe to Data Valid

120

asas

Address Setup to Address Strobe

ahas

Address Hold from Address Strobe

asrd

Address Strobe to RD Strobe

dvcs

Data Valid from RD

rdwi

RD Strobe Width

dhcs

Data Hold from RD

DP8496 Datasheet(PDF) 70 Page - National Semiconductor (TI)

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