DP8496 datasheet(12/92 Pages) NSC

12 / 92 page

30 Register List (Continued)

SPP SCSI Parity Polarity

Set to ‘‘1’’ when CRST is asserted or a SCSI Reset com-

mand is issued This is to prevent the parity bit from driving

the bus immediately after a reset while in Manual Mode

(Manual Mode described in Section 443)

Even parity is checked or generated on the SCSI bus if

enabled by the SPE bit

Odd parity is checked or generated on the SCSI bus if

enabled by the SPE bit

SPE SCSI Parity Enable

Set to ‘‘0’’ when CRST is asserted or a SCSI Reset com-

mand is issued Other than in Arbitration phase parity is

always provided when writing to the SCSI bus parity is

checked if buffer parity is being used (BPE e 1) or generat-

ed if buffer parity is not being used (BPE e 0) Parity verifi-

cation while reading the SCSI bus is dependent upon this bit

and some other variables as desribed below

SCSI Parity is verified on read data conditional to AM

bit of the SCSI Operation Register (43h) and HE bit of

the Synchronous Transfer Register (44h)as specified

in Table 34

SCSI Parity is never verified

TABLE 34 SCSI Parity

Auto

Handshake

When is parity checked during

a read from the SCSI bus

Man

Enable

Target Parity checked when

ACK asserted

Initiator Parity checked when

REQ asserted

(Re)Select Parity Checked while

SCSI ID matches SEL true BSY

false

Target Parity checked when

ACK asserted

Initiator Parity checked when

REQ asserted

Parity not checked

Refer to Table 410 in Section 429 for more detail on parity

SID(20) SCSI ID

The unique binary address which identifies the SCSI device

is loaded here This number is usually obtained by the proc-

essor after a Chip Reset from a PROM or from switches or

jumpers This is not to be confused with the LUN (Logical

Unit Number) of which each SCSI device can have eight

This field will be internally translated to the one-of-eight

form required for the SCSI bus

Setup 3 (SUP3)

62h

76543210

REV3

REV2

REV1

REV0

Asserting the CRST pin will not effect this register This reg-

ister must be initialized before proper interrupt operation

CI Combine Interrupts

Enabled Disk and SCSI interrupts appear on the DINT

pin The SINT pin is never asserted

Enabled Disk interrupts appear on the DINT pin En-

abled SCSI interrupts appear on the SINT pin

REV(30) Revision Number

These four bits reflect the functional version number of the

chip If a modification is made to the DP84967 that may

require software or hardware modifications in a system this

value will be modified as well The Revision Number corre-

sponding to this data sheet is 3h

The Revision Number will not be affected by a write to this

40 Functional Description

41 PROCESSOR INTERFACE

The processor port of the DP84967 can interface with

equal ease with NSCIntel-type and MotorolaZilog-type

processors An 8-bit multiplexed AddressData port is pro-

vided and through it the processor can randomly access all

SDDC registers The chip also provides two interrupt lines to

allow separate disk and SCSI interrupts

To the processor the DP84967 appears as a slave periph-

eral at all times and can be accessed with programmed IO

in memory mapped or IO mapped systems All control reg-

isters are eight bits wide Some functions are programmed

through more than one register For example address

pointers are accessed through three different registers be-

cause the address may be up to 22 bits wide The buffer

memory data is accessed through one register called the

Buffer Memory Data register (6Eh) There are two interrupt

registers in the DP84967 the SCSI Interrupt register (49h)

and the Disk Interrupt register (12h) Each of these interrupt

registers has an associated mask and status register

TABLE 41 DP8496DP8497 Address Map

Address

DP84967 Section

00 – 1F

Disk Data Controller

20 – 3F

Disk Format Registers

40 – 5F

SCSI Bus Controller

60 – 7F

Buffer Memory Setup

Timer

All the registers in the DP84967 have unique addresses

and most are readable and writable They can be accessed

in single instructions with a local processor The DP84967

never becomes a bus master on the processor bus

411 Access by Different Type Processors

At the time of chip reset the user can configure the

DP84967 to work with NSCIntel-type or MotorolaZilog-

type processors While the CRST pin is asserted the RDY

MODE pin functions as a MODE input This input will deter-

mine the processor access mode of the DP84967 If this

pin is left floating or pulled or driven high while CRST is

asserted the NationalIntel mode will be enabled If this pin

is pulled or driven low while CRST is asserted the Zilog

Motorola mode will be enabled

If NSCIntel-type mode is selected then pins RDiDS and

WRiRW act as Read Strobe and Write Strobe and they

are used to read and write data fromto the addressed reg-

ister If the MotorolaZilog-type mode is selected then the

same pins act as Data Strobe and ReadWrite where Data

Strobe is used to strobe data when reading or writing while

the direction of data is determined by the ReadWrite sig-

nal In either mode the address is strobed into the SDDC

with the ADSi signal

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