DP8496 datasheet(28/92 Pages) NSC

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40 Functional Description (Continued)

BMD Buffer Memory Data

Enables the Buffer Memory Data register Error interrupt

function Interrupt will occur when the processor has

read or written the Buffer Memory Data register too

quickly

Enables Buffer Memory Data Ready function (no inter-

rupt) The processor can poll the Disk Interrupt register

to see if enough time has passed to read or write to the

Buffer Memory Data register

HC Header Complete

Defines the HNC interrupt as ‘‘Header Complete’’

Defines the HNC interrupt as ‘‘Next Command’’

CCI Command Complete Interrupt

Enables all disk Command Complete Interrupts (CCI

field in the Disk Interrupt register)

Disables all disk Command Complete Interrupts

Sector Number (SN)

15h

76543210

Pattern

The contents of this register will replace any header byte

where the SN (Sector Number Substitution) bit is set to ‘‘1’’

in the corresponding Header Byte Control register This reg-

ister will be incremented after each sector operation is com-

pleted during a multi-sector command This register should

be initialized with the desired starting sector number for a

multi-sector command

This allows sequential logical sectors to be accessed during

multi-sector commands without processor intervention

Header Byte CountInterlock (HBC) 16h

76543210

Count

Count is the number of header bytes in the Header Seg-

ment The Count field must be loaded by the processor only

for a Format C or Format D command This count will allow

the Disk Data Controller to request the proper number of

header bytes from the buffer memory Allowable values for

count are 3 to 6 An even number of header bytes will al-

ways be transferred to and from buffer memory even though

only the specified count will be used in the header

This register is also used in interlock mode to signal com-

pletion to the Disk Data Controller if registers were updated

by the processor between sectors If the processor fails to

write to this register before the end of the sector when the

interlock mode is enabled a Late Interlock error will be gen-

erated and the disk operation will be aborted

Sector Count (SC)

17h

76543210

Count

Sets the number of sectors to operate on in a multi-sector

operation

Sector Count is really two registers called Active and Hold-

ing The holding register is down-loaded by the Disk Data

Controller to the active register at the same time a new

command is down-loaded from the Disk Command register

(just before the new command begins)

The Sector Count register is also down-loaded following the

last sector operation which decrements the active Sector

Count to zero This down-load will only occur if a new value

has been written to the Sector Count register after a previ-

ous down-load and before the zero detection If this down-

load occurs the current disk command will continue with

this new Sector Count

The processor may access either active or holding register

through this address as controlled by the AH (Ac-

tiveHolding) bit in the SCSI Operation register Normally

the processor should only access the holding register

ECC Control (EC)

07h

76543210

PRE

Span

PRE Preset Control

A zeros preset is used for all CRCECC calculations

A ones preset is used for all CRCECC calculations

This is the normal setting for most applications

DE Data Error Check Enable

This bit controls the verification of the CRCECC in the Data

Segment during a Read Ignore or Verify Data operation

Data field CRCECC is verified

Data field CRCECC is not verified

HE Header Error Check Enable

This bit controls the verification of the CRCECC in the

Header Segment during an Ignore Compare or Read Head-

er operation

Header field CRCECC is verified

Header field CRCECC is not verified

SPAN

Span bits 0 – 4 are set for the longest burst error that is to be

corrected Allowable values are 3 to 28 depending on poly-

nomial Values under 3 will default to 3 Refer to Table 418

in Section 434 for recommended values for SPAN This

value is only used during the Start Correction Cycle com-

mand

DP8496 Datasheet(PDF) 28 Page - National Semiconductor (TI)

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