DP8496 datasheet(59/92 Pages) NSC

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40 Functional Description (Continued)

This interrupt will be presented after the command has com-

pleted

While in Manual mode this error can only indicate a SCSI

parity error

Buffer Memory Parity Error

(011)

A parity error was detected while writing data to the SCSI

port from buffer memory This indicates a parity error in buff-

er memory This will terminate any SCSI command at the

end of the current transfer phase

The BME (Buffer Memory Parity Error) bit in the SCSI Status

Invalid Command

(100)

An invalid command for the present mode of the chip was

received in the SCSI Command register It is not guaranteed

that all invalid commands will be detected You should NEV-

ER issue an invalid command

Clearing an ‘‘Invalid Command’’ interrupt is a two-step pro-

cess First the APE (Arbitration Phase Enable) bit in the

SCSI Operation register should be modified twice (set then

reset or reset then set) Second clear the interrupt by writ-

ing the three-bit pattern (100) back to the SCSI Interrupt

Uncompleted Command

(101)

In Target mode this interrupt occurs when an Initiator sends

something unexpected For example the ATN signal re-

mains asserted after the first mesage byte in combination

commands or something other than a SCSI read command

is received in a Wait for SelectDisconnect command

When this completion interrupt is generated the SCSI

Status register will freeze in the state in which the SCSI bus

was in when the ‘‘Uncompleted Command’’ interrupt was

generated While in Initiator mode the actual phase may

now differ

When the ‘‘Uncompleted Command’’ interrupt is cleared

the SCSI Status register will return to normal operation and

will reflect the current status of the SCSI bus

The unexpected events include

While executing a ‘‘Wait for SelectDisconnect’’ com-

mand if a non-read SCSI Command Descriptor Block is

received

While executing a ‘‘Wait for Select’’ type command if a

message byte other than Identify is received or if a re-

served bit is not zero

While executing a ‘‘Wait for Select’’ type command if the

first byte of the Command Descriptor Block does not

map to a Group 0 1 2 or 5 type command

While executing any command if the ATN signal remains

asserted after the trailing edge of ACK on the last byte of

the Message Out phase

While executing a Message Out phase if the ATN signal

is deasserted before the leading edge of the REQ for the

last byte

While executing any information transfer phase if the

ATN signal is asserted

While executing a Reselect combination command if the

ATN signal is asserted during the Reselection phase if

the SE (Stop Enable) bit in the SCSI Operation register is

set to ‘‘1’’

While in a Message Out phase if the ATN signal be-

comes deasserted after REQ is false and while ACK is

true

While in a Message Out phase if the ATN signal be-

comes deasserted after both REQ and ACK are false

In the Initiator mode this interrupt will occur for an unex-

pected bus free condition It will also occur if the bus phase

changes after the first REQ is received The DP84967 rec-

ords the SCSI bus phase when the Target asserts REQ Any

change of the bus phase with REQ asserted will immediate-

ly terminate the current command with this interrupt

(Re)Selected

(110)

This interrupt could be generated without any SCSI com-

mand being issued The moment Automatic mode is en-

abled the DP84967 is susceptible to being (re)selected It

is also possible to (re)select the DP84967 after a SCSI

command has been issued by the processor

If the

DP84967 loses Arbitration and the winning device chooses

to select the DP84967 the chip will allow this and respond

properly

This interrupt will usually be unexpected and tell the proces-

sor that the DP84967 has responded to a Selection As a

Target the ATN line must be checked after receiving this

interrupt to determine if a Message Out phase is required

As an Initiator this interrupt would indicate a Reselection

from a Target

If a ‘‘Wait for Select’’ type command is currently executing

and waiting to be Selected it will terminate with an ‘‘Opera-

tion Complete’’ interrupt not a ‘‘(Re)Selected’’ interrupt

SCI Bus Reset

(111)

This interrupt could be generated without any SCSI com-

mand being issued A reset signal greater than one BCLK

period in length was received on the SCSI bus

The

DP84967 is now in Bus Free phase and any command

pending or executing has been terminated

Buffered Interrupts

The 3-bit Interrupt Code field can only present one type of

Interrupt at one time There may be occasions where more

than one interrupt has occurred If this is true then the first

interrupt that occurred will be reported by the Interrupt Code

field The second interrupt will be buffered internally When

the first completion code is cleared the buffered completion

code will be reported in the Interrupt Code field The SINT

pin will pulse inactive for a short period of time between

interrupts

The exception to this is the ‘‘No Error’’ completion interrupt

If this interrupt is generated it need not be cleared before

another completion interrupt is generated A new comple-

tion interrupt will overwrite any pending ‘‘No Error’’ comple-

tion interrupt This is summarized in Table 427

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