DP8496 datasheet(62/92 Pages) NSC

62 / 92 page

40 Functional Description (Continued)

TABLE 429 SCSI Bufer Management Interrupts

Block

New SCSI

New Block

Count

Command

Count Been

Interrupt

Comments

Reached

Been

Loaded

Type

Zero

Loaded

BTC

Single block transfer complete

Yes

GTC

The last block of the Group has been transferred tofrom the SCSI Bus

Command is extended with new Block Count

Yes

CCI

Previous SCSI command has completed New pipelined command is

starting

Yes

CCI

Previous SCSI command has completed No new command

Note

BTC e Single Complete Interrupt GTC e Group Complete Interrupt CCI e Command Complete Interrupt

Automatic Mode

The Automatic Mode transfers data between the SCSI bus

and external buffer memory using internal DMA The Auto-

matic Mode is enabled by setting the AM (Automa-

ticManual) bit in the SCSI Operation register

If the Synchronous Transfer register is set for synchronous

transfers the transfer mode will automatically change be-

tween synchronous and asynchronous depending on the in-

formation transfer phase if the DP84967 is configured as a

Target If configured as an Initiator the Synchronous Trans-

fer register must be setup correctly for the phase prior to

issuing the Transfer Info command

Transfers of odd byte blocks are allowed in both Asynchro-

nous and Synchronous modes However the SCSI FIFO will

be flushed after each block transferred if the block size is

odd in word mode Therefore the maximum data transfer

rate will be achieved only for transfers of even byte counts

while in word mode While in byte mode odd and even

transfers are equally fast

In both synchronous and asynchronous transfer modes

successive requests or acknowledges cannot occur faster

than two bus clock cycles apart If this condition occurs a

‘‘SCSI Bus Error’’ interrupt will be generated and a ‘‘SCSI

Data Overrun’’ error code will be set in the SCSI Status

Manual Mode Information Transfer

Manual Mode is enabled by clearing the AM (Automatic

Manual) bit in the SCSI Operation register This is the de-

fault mode after a CRST or a SCSI Reset Command While

in this mode all the commands in the SCSI Command regis-

ter become unavailable This mode is intended to accom-

modate lower level processor controlled transfers which

may be unique to an application In other words the SCSI

protocol becomes completely processor controlled

A typical sequence may be to issue a (Re)Select command

in the Automatic Mode since this is not easy or fast in the

Manual Mode then switch to Manual Mode for further per-

haps unique transfers or phase sequences

Data can then be transferred in two different ways while in

Manual Mode By setting the HE (Handshake Enable) bit in

the Synchronous Transfer register to a ‘‘0’’ the SCSI data

bus appears as a simple transceiver without a latch This

mode is intended for unique applications which require proc-

essor control over the Arbitration and Selection phases

Data written to the SCSI Data register will be asserted im-

mediately on the SCSI bus and data read from the SCSI

Data register will be an exact and immediate reflection of

the SCSI bus

By setting the HE bit to a ‘‘1’’ the SCSI Data register be-

comes latched and the processor can easily transfer single

bytes of data The DBR (Data Buffer Ready) bit in the SCSI

Status register should be polled to pace the data transfer If

sending data out of the DP84967 the DBR bit should be

polled for a ‘‘0’’ This indicates the SCSI Data register is

empty and ready for another byte to be sent If receiving

data into the DP84967 the DBR bit should be polled for a

‘‘1’’ This indicates the SCSI Data register is full and a byte

is ready to be read by the processor

A Few Cautions

(while in Manual Mode)

If the DP84967 is a target receiving information from the

SCSI Bus then the processor should switch the IO line

before reading the last byte

This is to prevent the

DP84967 from issuing another REQ and causing a DMA

overrun condition on the Initiator side

If in Manual Mode and not active on the SCSI bus several

conditions must be met to prevent the DP84967 from driv-

ing the SCSI bus or causing unexpected error conditions

within itself The HE (Handshake Enable) bit in the Synchro-

nous Transfer register must be 0 the SCSI Data register

must be 00 the SPP (SCSI Parity Polarity) bit in the Setup 2

up upon assertion of the CRST pin or a SCSI Reset com-

mand Be sure that these conditions are set up before

switching the AM bit from Automatic to Manual Mode

If connected as a Target in Manual Mode REQ is asserted

as soon as the HE (Handshake Enable) bit in the Synchro-

nous Transfer register is switched from ‘‘0’’ to ‘‘1’’

Note that no DMA transfers occur between the SCSI bus

and buffer memory while in Manual Mode

While in Manual Mode there is no automatic protection

against generating illegal SCSI operations Care should be

taken to ensure that other devices on the SCSI bus are not

adversely affected by custom sequences

Differential Transceiver Control in Manual Mode

On the DP8497 fourteen pins are dedicated to the task of

controlling the direction of off-chip differential transceivers

required for Fast SCSI type applications Control of these

DP8496 Datasheet(PDF) 62 Page - National Semiconductor (TI)

DP8496 Datasheet(HTML) 62 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL