DP8496 datasheet(14/92 Pages) NSC

14 / 92 page

40 Functional Description (Continued)

The maximum capacitive loading on the Buffer Memory In-

terface should be taken into account when designing the

buffer memory interface The addressdata pins are de-

signed to directly drive up to 12 DRAM chips with board

traces of reasonable length By using 256k x 1 chips 256k

can easily be addressed in 8-bit mode By using higher den-

sity DRAMs like 1M x 4 and 1M x 1 the full addressing

range of 4M in byte-wide mode and 2M in word-wide mode

can be utilized with chip counts up to or less than 12

No refresh address counters are provided on-chip This ne-

cessitates the use of DRAMs with on-board counters and

the ability to do a ‘‘CAS before RAS’’ type refresh

423 Data Transfer Timing

Two basic transfer modes are possible normal mode and

the fast page mode If the fast page mode is disabled by

setting the DFP bit to 1 in Setup 1 register (60h) then a

single memory transfer will occur every 5 BCLK cycles for

DRAM and every 5 or 6 cycles for SRAM depending on the

SWS bit of the SUP1 register

If the fast page mode is selected by setting the DFP bit to 0

then the DP84967 will transfer up to 6 bytes (or 4 words in

word-mode) of data at a time in a ‘‘burst’’ as long as only

the least significant 8 bits of address change In the case of

DRAMs then the DP84967 only has to change the ad-

dress and toggle the CAS line for each byte or word of the

burst transferred after the first one The number of bytes or

words transferred in a ‘‘burst’’ are shown in Table 46 and

depend on number of bytes or words present in the on-chip

FIFOs the address pointers’ relation to the page boundary

and refresh etc Operation in this mode yields highest at-

tainable buffer memory bandwidths but it requires the use

of fast page mode type DRAMs

TABLE 46 Fast Page Mode Transfer Periods

Number of

DRAM

SRAM

Transfers

Transfer

Period

6 Bytes

12 BCLK Period

17 BCLK Pd (SWS e 0)

23 BCLK Pd (SWS e 1)

4 Bytes

9 BCLK Period

1 Byte

5 BCLK Period

4 Words

9 BCLK Period

12 BCLK Pd (SWS e 0)

16 BCLK Pd (SWS e 1)

3 Words

8 BCLK Period

2 Words

6 BCLK Period

1 Word

5 BCLK Period

Note

SWS is bit 5 in SUP1 register (60h)

The DP84967 issues a DRAM refresh cycle every 128 bys

clock periods Of these 5 bus clock periods are used by the

refresh cycle to complete so 123 bus clock periods are left

for actual data transfers Thus the minimum specified bus

clock rate of 10 MHz will guarantee a refresh cycle time of

less than 128 ms per row

The DP84967 automatically manages concurrent buffer

accesses by disk SCSI and processor while also executing

DRAM refresh cycles within the requisite time Small FIFO’s

have been integrated into the DP84967 to allow for buffer

memory latency due to contention The Disk Data Controller

has a 14 byte (or 7 word) FIFO and the SCSI Bus Controller

has a 32 byte (or 16 word) FIFO The word-wide FIFOs are

used if the 16-bit mode is used for buffer memory

The on-chip arbitration circuitry uses the prioritization

scheme shown in Table 47 to smoothly manage the data

flow and insure that the FIFOs don’t overflow or underflow

TABLE 47 Buffer Memory Transfer Priority

Rank

Type of Transfer

DRAM Refresh

Disk Data Burst

SCSI Data Burst

Processor Access

Disk DataSingle ByteWord

SCSI DataSingle ByteWord

Idle

The DP84967 arbiter does not waste any cycles between

consecutive transfers even if those transfers used different

pointers Pointers are seamlessly switched so that all mem-

ory transfers use consecutive BCLK cycles

Keeping in mind the above priority scheme some design

trade-offs must be made between the available bandwidth

of the buffer memory port and rates of disk SCSI and proc-

essor accesses that are to be supported A sound design

would assure that enough bandwidth is left over after ac-

commodating simultaneous full-speed disk and SCSI trans-

fers so that occasional processor access can be serviced

within reasonable time Section 426 describes how proces-

sor accesses of buffer memory are handled

Detailed timing specifications for the buffer memory port

can be found in Chapter 6 of this document For a given bus

clock frequency calculations for gross available bandwidth

can be carried out by using Table 46 For example with bus

clock frequency set at 20 MHz and with 6 bytes of fast-

page mode transfers taking 12 cycles

bandwidth of

10 MBytesec is calculated for a byte-wide operation How-

ever after this number is adjusted for the DRAM refresh

cycle

overhead

maximum

bandwidth

reduced

96 MBytesec There are other practical factors that would

further reduce this number to the attainable sustained

bandwidth for a particular transfer For the case of BCLK e

20 MHz this value turns out to be 93 MHz

As a calculation based on the timing specifications in Chap-

ter 6 would show 100 ns DRAMs would work with the

DP84967 operating with bus clock of 20 MHz By using

faster BCLK and DRAMs the user can achieve sustained

byte-wide bandwidths of above 11 MBytesec

TABLE 48 DRAM Bandwidth Capabilities

Desired

DRAM

Fastest Usable

BCLK

Attainable Bandwidth

Byte-Wide

Word-Wide

100 ns

18 MHz

84 MHz

153 MHz

100 ns

20 MHz

93 MHz

170 MHz

80 ns

22 MHz

102 MHz

187 MHz

80 ns

24 MHz

112 MHz

204 MHz

The maximum BCLK frequency is specified in Chapter 7

For maximum performance however word-wide memory

architecture can be employed

and then

with 100 ns

DRAMs and 20 MHz BCLK

sustained bandwidth of

17 MBs can be attained

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