DP8496 datasheet(7/92 Pages) NSC

7 / 92 page

20 Pin Description (Continued)

Symbol

Type

Function

SCSI BUS TRANSCEIVER DIRECTION CONTROL PINS

(DP8497 Only)

DSDB07

48 – 56

DIRECTION CONTROL FOR SCSI DATA PARITY BUS

Each of these signals connects to

the appropriate enable pin of the differential transceivers used for a Fast SCSI

DSDBP

implementation and controls the direction of its corresponding SCSI data bus signal A high

level on these pins enables the driver while a low level enables the receiver

DTARG

DIRECTION CONTROL FOR TARGET SIGNALS

Same as above Controls the direction of

CD IO REQ and MSG signals

DINIT

DIRECTION CONTROL FOR INITIATOR SIGNALS

Same as above Controls the direction

of ACK and ATN signals

DBSY

DIRECTION CONTROL FOR BSY

Same as above Controls the direction of BSY signal

DSEL

DIRECTION CONTROL FOR SEL

Same as above Controls the direction of SEL signal

DRST

DIRECTION CONTROL FOR RST

Same as above Controls the direction of RST signal

BUFFER MEMORY INTERFACE PINS

DB1 – 07

84 – 92

DATA BUS 1

These nine active high bi-directional lines transfer data between the

DP84967 and the least significant 8-bits plus parity of buffer memory

DB1–P

ADB2 – 07

93 – 97

ADDRESS DATA BUS 2

These nine active high bi-directional lines transfer data between

the DP84967 and the most significant 8-bits plus parity of buffer memory if word mode is

ADB2 – P

99 – 100

enabled These pins also contain address information for static RAM See Tables 42 and

1–2

AB3 – 07

4 – 11

ADDRESS BUS 3

These eight active high outputs represent address information for both

SRAM and DRAM See Tables 42 to 45

AB4 – 02

12 – 14

ADDRESS BUS 4

These three active high outputs represent address information for both

SRAM and DRAM See Tables 42 to 45

RDo or

The function of this pin is determined by the use of SRAM or DRAM

CAS

READ STROBE (OUT)

SRAM

COLUMN ADDRESS STROBE

DRAM

WRo19

WRITE STROBE (OUT)

Always

ADSo or

The function of this pin is determined by the use of SRAM or DRAM

RAS

ADDRESS STROBE (OUT)

SRAM In word mode controls address latch for ADB2 bus

High level on this signal should be used by an external latch to accept address inputs

latching them on the falling edge

ROW ADDRESS STROBE

DRAM

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