DP8496 datasheet(60/92 Pages) NSC

60 / 92 page

40 Functional Description (Continued)

TABLE 427 Interrupt Buffering

TLF11212 – 34

SCSI Interrupt Enable (SINTE)

4Ah

76543210

PCMP

ATN

GTC

BTC

LCI

This register simply enables selected interrupts to physically

assert the SINT pin If an interrupt is disabled via this regis-

ter all the effects of the interrupt remain the same except it

will not affect the SINT pin

Bits 3 – 7 enable individual checkpoint type interrupts A ‘‘1’’

allows the individual interrupt to assert the interrupt pin A

‘‘0’’ prevents it

The CI (Completion Interrupts) bit allows all completion type

interrupts to assert the interrupt pin The completion inter-

rupts cannot be enabled individually

Interrupts should be cleared from the SCSI Interrupt register

whether or not they are enabled in the SCSI Interrupt En-

able register

SCSI Block Count (SBC)

4Bh

76543210

Count

The value programmed in this register sets the number of

blocks to be transferred A value of 00h means 256 blocks

This value in conjunction with the block size value in SBSH

and SBSL registers determines the total number of bytes to

be transferred

SCSI Block SizeHigh (SBSH)

4Ch

76543210

SizeHigh Order Byte

SCSI Block SizeLow (SBSL)

4Dh

76543210

SizeLow Order Byte

The size of the user’s SCSI blocks is programmed in these

two registers This value in conjunction with the block count

value in the SBC register determines the total number of

bytes to be transferred

Differential SCSI 1 (SDIF1)

4Eh

76543210

DCSDB7 DCSDB6 DCSDB5 DCSDB4 DCSDB3 DCSDB2 DCSDB1 DCSDB0

Differential SCSI 1 (SDIF1)

4Fh

7654

SCK1

SCK0

DCBSY DCSEL DCTARG DCINIT DCRST DCSDBP

(Other than the SCK1 and SCK0 bits all other bits are meaningful only on

the DP8497)

DCSDB(70) DCSDBP

The polarity of each of these bits sets the polarity of the

DSDB(70) and DSDBP pins of the DP8497 and also the

direction of the on-chip transceiver at the associated signal

pin thus providing differential transceiver direction control

to the user in manual mode operation A ‘‘1’’ in any of these

bits and therefore a high level on the corresponding direc-

tion control pin means the transceivers are in ‘‘drive’’

mode while a ‘‘0’’ signifies the ‘‘receive’’ mode

In effect only during manual mode

DP8496 Datasheet(PDF) 60 Page - National Semiconductor (TI)

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