DP8496 datasheet(55/92 Pages) NSC

55 / 92 page

40 Functional Description (Continued)

The SCSI Data register is simply a transparent latch

between the SCSI bus and the processor The REQ

and ACK signals are not automatically asserted REQ

and ACK (and other SCSI control signals) may be modi-

fied by the processor through the SCSI Control register

Parity is not verified when reading data from the SCSI

bus Parity is always generated when writing to the

SCSI bus

For information transfers it is not recommended to use

HE e 0 because parity is not checked

Transfer Period

This field determines the time between adjacent Synchro-

nous Data transfers It is also used to choose between Syn-

chronous and Asynchronous Transfer modes

A value of zero will give Asynchronous Transfers with fast

handshaking between REQ and ACK A value of one will

give Asynchronous Transfers an extra BCLK period per

REQ and ACK handshake (It is also possible for the user to

set the setup time delay between REQ and ACK and the

SCSI data signals by setting the SCK1 and SCK0 bits of the

Differential SCSI 2 register)

A value of two to seven enables Synchronous Transfers

with a Transfer Period (TP) equal to BCLK period multiplied

by the value programmed (2 – 7)

While in the Target Mode if a non-Data Phase is executing

Asynchronous transfers will be used regardless of the value

in this field This is done because Synchronous transfers are

only allowed during the Data In Phase and the Data Out

Phase

Caution

While in Initiator Mode the DP84967 will NOT

automatically switch between Synchronous and Asynchro-

nous modes This must be switched by the processor

Table 423 summarizes the transfer mode used based on

this field and the phase in progress

The value in this field along with the BCLK frequency also

determines the DP84967s adherence to other synchro-

nous SCSI timing specificationsREQ assertion period

(90 ns 30 ns for Fast) REQ negation period (90 ns 30 ns

for Fast) DATA setup time (55 ns 25 ns for Fast) and Data

Hold Time (100 ns 35 ns for Fast) The equations for these

times are specified in the AC Specification section of this

datasheetin subsections 629 thru 632 Maximum BCLK

is specified in subsection 61

TABLE 423 Transfer Mode and Period

Trns

Prd

Current SCSI Phase of DP8496DP8497

Target Data In

Target All Phases

Target Data Out

EXCEPT Data In and

Initiator All Phases

Data Out

Async

Slow Async

Sync TP e 2 BCLK

Async

Sync TP e 3 BCLK

Async

Sync TP e 4 BCLK

Async

Sync TP e 5 BCLK

Async

Sync TP e 6 BCLK

Async

Sync TP e 7 BCLK

Async

Notes

TP e Transfer Period

See AC Timing for Async vs Slow Async

TLF11212 – 33

FIGURE 420 Synchronous Transfer Period

Offset

The offset value specifies the number of outstanding bytes

allowed before handshaking is inhibited A value of zero re-

sults in an offset of 16

If the Block Count register is greater than one or if the

Block Count is pipelined the offset value must not be great-

er than the Block Size registers Otherwise data may be

written to buffer memory incorrectly If the Block Count is

one and there is no pipelining then there is no restriction

on the value of the offset

Identify (IDENT)

45h

765

3210

DISC

TAR

Reserved

LUN

The Identify register is used only with Reselect combination

and ‘‘Wait for Select’’ type commands This is actually a

simple 8-bit register with no fixed structure All of the bits

may be read and written by the processor However in most

applications the bit definitions should correspond with the

ANSI SCSI specification

The Reselect combination commands use the contents of

the Identify register during the Message In phase following

Reselection The processor must load the Identify register

before a Reselect combination command is issued

The ‘‘Wait for Select’’ commands modify the Identify regis-

ter This byte is received from the Message Out phase after

a connection The data here is valid as soon as the mes-

sage phase is completed although the processor is not no-

tified with an interrupt until the entire command is complete

The Identify register is overwritten upon the next ‘‘Wait for

Select’’ operation or when the processor loads the Identify

Caution

This register must be initialized with a valid value

after a reset before any command is written to the SCSI

Command register

Otherwise an ‘‘Uncompleted Com-

mand’’ interrupt will be generated A valid value is any value

with bit 7 set and bits 3 and 4 cleared

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