DP8496 datasheet(67/92 Pages) NSC

67 / 92 page

50 Application Information Buffer Memory Interfacing

in a Fast SCSI Implementation (Continued)

There is also a PAL programmed to provide the chip select

signals Additionally the HPC46003 has many input and

output pins available for drive control

The disk connections are straight forward The disk control-

ler accepts the unencoded NRZ from any encoderdecoder

here the 17 ENDEC is shown The Read channel is the last

block before the head’s preamp This schematic shows only

those read-channel connections that apply to the disk con-

troller portion of the disk

The ‘96B97 have an advanced SCSI controller

This

means the on-board mController does not need extremely

sophisticated firmware for controlling the SCSI interface

They also have high level disk control commands The

Controller can just issue simple commands with no further

need for intervention

To set up the DP8496DP8497 a few registers need to be

initialized The first setup register is SUP1 at 60h The bits in

this application are defined as

Bit

Name

Description

7 6

CLK (10)

These two bits are set to 01 for a

20 MHz bus clock

SWS

This bit is for SRAM wait states it does

not apply to systems using DRAMs for

their buffer memory Here it is set to 0 as

a default

DFP

This bit when set disables the use of

fast page mode DRAMs Here it is set to

0 because fast page mode is necessary

to acheive the high bandwidth

3 2

DD (10)

These bits select the DRAM size Since

256k x 16’s are used the values for

these bits should be 01

RSEL

This is the RAM select bit Here it is 1 to

select DRAMs

RWID

RAM Data Path Width Here it is 0 for

word mode

Therefore the value to load at 60h in the DP8496DP8497 is

01000110 or 46h

The setup register SUP2 is concerned with how the proces-

sor accesses are performed and the enabling and type of

parity for the buffer and SCSI interfaces Here it is loaded as

follows

Bit

Name

Description

Auto Increment Depends on how the proc-

essor wants to access the buffer memory

Since it depends on the software it is set to

0 here for example

BPP

Buffer Parity Polarity Even parity is chosen

arbitrarily so this bit is set to 1

BPE

Buffer Parity Enable This isa1to enable the

buffer memory parity checks

SPP

SCSI Parity Polarity Here Odd parity is cho-

sen so the bit is set to 0

SPE

SCSI Parity Enable This is set to 1 to check

the parity on the SCSI bus when the condi-

tions are met

2 – 0

SID

SCSI ID This is set in this example to be 110

(6) to make it the next highest priority after

the initiator This is a good priority for a boot

drive But typically the mC’s firmware will set

this value based on switches or jumpers set

by the user

Thus the value to be written to the SUP2 register at 61h is

01101110 or 7Eh

The third setup register SUP3 has only one bit to set for this

configuration The bit is the CI bit the Combine Interrupts

bit It is 0 to make the disk related interrupts appear on the

DINT pin and the SCSI related interrupts to appear on the

SINT pin Therefore a value of 00 should be written to the

SUP3 register at 62h

The DP8496DP8497 devices are extremely efficient in pro-

viding high speed disk control and a SCSI interface The

disk control and interface functions in this application of a

512 KByte buffer Fast 10 MBytessec differential SCSI

and a high performance mController can be made using only

12 chips

TLF11212 – 8

FIGURE 52

DP8496 Datasheet(PDF) 67 Page - National Semiconductor (TI)

DP8496 Datasheet(HTML) 67 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL