DP8496 datasheet(35/92 Pages) NSC

35 / 92 page

40 Functional Description (Continued)

The altered format registers will apply to the next sector to

be operated on regardless of whether the drive command

is a multi-sector type or not

A new drive command may also be loaded along with updat-

ing the Format registers This would facilitate a Read Head-

erRead Data command (to locate track position) followed

by a Compare HeaderRead Data command (multi-sector)

to read the rest of the track See the previous sub-section

for a description of how commands are pipelined

Changing disk format registers other than the ones listed

above can have critical timing restrictions In general if the

field to be changed for the next sector has been or is being

written to disk for the current sector it is safe to change the

count and pattern registers for that field

The ‘‘Header Complete’’ interrupt is enabled by setting the

HNC (Header CompleteNext Command) bit in the Disk

Interrupt Enable register to a ‘‘1’’

Single Sector Formatting

Format operations normally start with an index pulse and

end with the next index pulse thus formatting one track

Individual sectors can be formatted for hard sectored drives

only via the Write HeaderWrite Data command A Com-

pare HeaderRead Data may be issued before the Write

HeaderWrite Data command to locate the sector preced-

ing the sector to be formatted

AMFAME Operation

Address mark found (input) and address mark enable (out-

put) pins are usually used with soft sectored drives to syn-

chronize the actual disk with DP84967 data operations On

true soft sectored drives (ST506412 type) AME is generat-

ed for each byte of Synch

1 generated during a format or

write operation On a compare or read operation AMF

is expected for each Synch

1 byte read In MFM systems

this is commonly generated by a missing clock from an A1h

byte

In the pseudo-hard sectored mode AME is used to perform

two different functions During a format AME is asserted

during the Header Gap field This along with the fact that

WGATE was already asserted instructs the drive to write an

Address Mark (the Header Gap Count should be loaded

with a 3 according to the ANSI draft proposed ESDI specifi-

cation) During a read or write data operation AME is assert-

ed after the specified starting condition for a soft sectored

drive (immediately wait for index wait for timer etc) The

Disk Data Controller will then wait for AMF to be asserted by

the drive before executing the command AME will be as-

serted again before each sector operation and the Disk

Data Controller will wait for the AMF before continuing

Table 417 shows the proper state for the HSS and DT bits

(HardSoft Sectored and Drive Type) in the Disk Control

Disk Data Error Handling

The DP84967 uses a fixed 32 48 or 56-bit ECC polynomial

for detection and correction of errors Correction is per-

formed entirely on-chip with one of the fixed polynomials

The processor needs only to EX-OR the correction mask

bytes contained on-chip after a successful correction cycle

with the bytes in error in buffer memory

It is not recommended to use the maximum correction span

listed in Table 418 The chance for a mis-correction is too

great The recommended correction span produces the

best trade-off between correction span and probability of

mis-correction The correction span is set in the ECC Con-

trol register

TABLE 417 Drive Types

Drive Type

Operation

HSS

PSIG

AME Asserted

AMFSector

If IS Set to ‘‘1’’

Written

during

Pulse Expected

Int Generated

Soft Sectored

Format

First Sector

Hdr Synch

ST506 Type

of Track

Data Synch

Format

Write

Data Synch

Hdr Synch

Index

Read

Never

Hdr Synch

Data Synch

Pseudo Hard

Format

First Sector

Hdr Gap

Index

Sectored

of Track

(ESDI Soft

Write

ESDI Handshake

AMF for ESDI

Sectored)

Handshake

Index or AMF

Using Gap Type

Read

ESDI Handshake

AMF for ESDI

Address Mark

Handshake

Hard Sectored

Format

All Sectors

Never

Sector

Index or Sector

Not Using Gap

Format

All Sectors

Post SectorIndex

Sector

Type Address

Gap

Mark

Write

Never

Sector Pulse

Read

Never

Sector Pulse

Note

IS (IndexSector) bit is in Disk Control register If the IS bit is set to ‘‘0’’ an interrupt is generated at each Index pulse only

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