DP8496 datasheet(3/92 Pages) NSC

3 / 92 page

10 Overview

The DP84967 contains four major sections Each section is

listed below along with the major functions performed within

that section

1 Processor Interface

Processor Interface for chip control

2 Buffer Memory Interface

SRAMDRAM control timing

Memory access arbitration

Memory access prioritization

3 Disk Data Controller

SerializerDeserializer (SERDES)

ReadWriteFormat Control

CRCECC generationcheckingcorrecting

4 SCSI Bus Controller

SCSI Data Transfer Control

SCSI Bus Controlphase changes

Parity generationchecking

On-chip bus transceivers

The Processor Interface section allows the drive’s proces-

sor access to all programmable features of the chip This

interface is used to initiate and control any function or oper-

ation on both disk and SCSI data All DP84967 registers

are accessed through this section

Buffer RAM is needed for all disk or SCSI data transfers

This RAM is connected to the Buffer Memory Interface sec-

tion The DP84967 assumes exclusive access to this buffer

RAM This enables the chip to utilize the full bandwidth of

the RAM to streamline any combination of disk SCSI or

processor transfers All transfer of data is done with on-chip

DMA Address pointers may be pipelined which will allow

different groups of data to be placed in non-consecutive

locations in buffer memory

The Disk Data Controller section transfers NRZ data to the

serial disk data path Sector size gaps synch bytes etc are

programmable It can work with hard or soft sectored drives

ESDI soft sectored (pseudo-hard) AMFAME handshaking

is programmable Fixed 324856-bit ECC polynomial hard-

ware automatically generates and checks error correction

fields Correction calculation is done on chip which will re-

lieve the processor of the time and code space overhead of

this function

The SCSI Bus Controller section saves the user board area

by integrating the 48 mA open drain drivers The controller

was designed to minimize the number of interrupts generat-

ed due to phase changes parity errors and the like Groups

of often used phase sequences can be invoked with a sin-

gle command

An internal timer is also available on the DP84967 which

may be used to accurately control the execution of certain

commands for the disk or SCSI sections

Block Diagram

TLF11212 – 2

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