AMD-761 datasheet(18/264 Pages) AMD

18 / 264 page

Overview

Chapter 1

AMD-761™ System Controller Software/BIOS Design Guide

24081D—February 2002

Preliminary Information

DDR PDL Calibration Control

Dev 0:F1:0x40

SW_Recal

[7]

Use_Act_Dly

[6]

Auto_Cal_En

[5]

Act_Dly_Inh

[4]

Auto_Cal_Period

[1:0]

DDR PDL Configuration 0–17

Dev 0:F1:0x44

through

Dev 0:F1:0x88

Clk_Dly

[31:24]

SW_Cal_Dly

[23:16]

Cal_Dly

[15:8]

Act_Dly

[7:0]

DDR DQS/MDAT Pad Configuration

Dev 0:F1:0x8C

PSlewMDAT

[29:27]

NSlewMDAT

[26:24]

PDrvMDAT

[19:18]

NDrvMDAT

[17:16]

PSlewDQS

[13:11]

NSlewDQS

[10:8]

PDrvDQS

[3:2]

NDrvDQS

[1:0]

DDR CLK/CS Pad Configuration

Dev 0:F1:0x90

PSlewCLK

[29:27]

NSlewCLK

[26:24]

PDrvCLK

[19:18]

NDrvCLK

[17:16]

PSlewCS

[13:11]

NSlewCS

[10:8]

PDrvCS

[3:2]

NDrvCS

[1:0]

DDR CMDB/CMDA Pad

Configuration

Dev 0:F1:0x94

PSlewCMDB

[29:27]

NSlewCMDB

[26:24]

PDrvCMDB

[19:18]

NDrvCMDB

[17:16]

PSlewCMDA

[13:11]

NSlewCMDA

[10:8]

PDrvCMDA

[3:2]

NDrvCMDA

[1:0]

Table 1.

AMD-761™ System Controller Configuration Register Bits Unknown at RESET# (Continued)

Offset

Bit Name

Bit(s)

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