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AMD-761 Datasheet(PDF) 76 Page - Advanced Micro Devices |
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AMD-761 Datasheet(HTML) 76 Page - Advanced Micro Devices |
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76 / 264 page  64 AMD-761™ System Controller Programmer’s Interface Chapter 2 AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Preliminary Information BIU0 SIP Dev0:F0:0x64 Register Description This register provides visibility to the serial initialization packet delivered to the AMD Athlon™ processor during the AMD Athlon processor system bus connect protocol. 31 30 29 28 27 26 25 24 Bit Clk_Fwd_Offset Data_Init_Cnt Addr_Init_Cnt Sys_Data_Even_Clk_Dly Reset 0 Pinstrapping R/W R/W R 23 22 21 20 19 18 17 16 Bit Sys_Data_Odd_Clk_Dly Sys_Data_Even_Dly Sys_Data_Odd_Dly Sys_Addr_Dly Reset Pinstrapping R/W R 15 14 13 12 11 10 9 8 Bit Sys_Addr_Dly SysDC_Dly Sys_Addr_Clk_Dly Reset Pinstrapping R/W R 7 6 5 4 3 2 1 0 Bit Sys_Rst_Clk_Offset Sys_Data_Rec_Mux_PreLd Sys_Addr_Rec_Mux_PreLd Reset 0 0 Pinstrapping R/W R |
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