AMD-761 datasheet(65/264 Pages) AMD

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Chapter 2

AMD-761™ System Controller Programmer’s Interface

24081D—February 2002

AMD-761™ System Controller Software/BIOS Design Guide

Preliminary Information

25-24

tWR

Write Recovery Time

This bit field controls the number of clock cycles that must occur from the last valid

write operation to the earliest time a new precharge command can be asserted to the

same bank.

00 = tWR duration is 1 clock cycle.

01 = Reserved

10 = tWR duration is 2 clock cycles.

11 = tWR duration is 3 clock cycles.

tRRD

Activate Bank A to Activate Bank B Command Delay

This bit controls the number of clock cycles between successive activate commands to

different banks.

0 = tRRD duration is 2 clock cycles.

1 = tRRD duration is 3 clock cycles.

22-19

Reserved

18–16

Idle_Cyc_Limit

Idle Cycle Limit

This bit field controls the number of idle cycles to wait before precharging an idle bank.

Idle cycles are defined as cycles in which no valid requests are asserted.

111 = Disable idle precharge

110 = 48 cycles

101 = 32 cycles

100 = 24 cycles

011 = 16 cycles

010 = 12 cycles

001 = 8 cycles (recommended “safe” configuration)

000 = 0 cycles

15–14

PH_Limit

Page Hit Limit

This bit field controls the number of consecutive page hit requests to allow before

choosing a non-PH request.

00 = 1 cycle

01 = 4 cycle

10 = 8 cycles (recommended “safe” configuration)

11 = 16 cycles

13–12

Reserved

Bit Definitions (Continued)

DRAM Timing (Dev0:F0:0x54)

Bit

Name

Function

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