AMD-761 datasheet(22/264 Pages) AMD

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AMD-761™ System Controller Programmer’s Interface

Chapter 2

AMD-761™ System Controller Software/BIOS Design Guide

24081D—February 2002

Preliminary Information

2.2

Address Map

Table 3 shows the address map implemented by the AMD-761™

system controller.

Table 3.

AMD-761™ System Controller Socket2000 Memory Map

Address Space Start Address Space End

Name/Command

Description

SysAddOut MSB =0

1 FF000 0000

SysAddOut MSB

=0 &

3 FFFF FFFF

Reserved

(Masked)

May be used by the Northbridge for other

purposes (used for EV6 Northbridges).

SysAddOut MSB =0

1 FE00 0000

SysAddOut MSB

=0 &

1 FEFF FFFF

PCI Configuration

Space

(Masked)

This space is used to create PCI configuration cycles

using WrBytes, WrLWs, RdBytes, and RdLWs

commands only. See Section 2.2.3 on page 15.

SysAddOut MSB =0

1 FC00 0000

SysAddOut MSB

=0 &

1 FDFF FFFF

PCI I/O Space

(Masked)

This space is used to create PCI I/O cycles using only

WrBytesWrLWs, RdBytes and RdLWs commands.

SysAddOut MSB =0

1 F800 0000

SysAddOut MSB

=0 &

1 FBFF FFFF

PCI IACK/Special

Cycle Generation

(Masked)

WrLWs commands to this space are used to create

PCI special cycles. The lower 16 bits of the data is

passed on to the PCI bus as both the address and

data with the special cycle PCI command. See

Section 2.2.1 on page 12 for all special cycles

generated by the AMD Athlon™ processor.

RdBytes commands to this space are used to

create PCI IACK. The lower 16 bits of these

addresses are passed on unmodified to the PCI

with the IACK PCI command. See Section 2.2.2 on

page 15.

SysAddOut MSB =0

1 0000 0000

SysAddOut MSB

=0 &

1 F7FF FFFF

Reserved

(Masked)

May be used by the Northbridge for other

purposes (used for EV6 Northbridges).

SysAddOut MSB =0

0 0000 0000

SysAddOut MSB

=0 &

0 FFFF FFFF

PCI Memory Space

(Masked)

The lower 32 bits of these addresses are

forwarded unmodified to the PCI. Accessed only

with Wr/RdBytes, Wr/RdLWs, Wr/RdQWs. The

AMD-761™ system controller generates low-order

address bit as required from the AMD Athlon

processor system bus MASK field.

SysAddOut MSB =1

0 0000 0000

SysAddOut MSB

=1 &

3 FFFF FFFF

Normal Memory

(Masked Writes)

DRAM, accessed only with masked write

commands WrBytes, WrLWs, WrQWs.

SysAddOut MSB =1

0 0000 0000

SysAddOut MSB

=1 &

3 FFFF FFFF

Reserved

(Masked Reads)

The AMD-761 system controller does not support

masked reads to this address space.

SysAddOut MSB =1

0 FF000 0000

SysAddOut MSB

=1 &

3 FFFF FFFF

Reserved

(Blocks)

May be used by the Northbridge for other

purposes (used for EV6 Northbridges).

SysAddOut MSB =0

0 0000 0000

SysAddOut MSB

= 0 &

3 FFFF FFFF

Normal Memory

(Blocks)

DRAM, accessed with read and write block

commands. Note that the AMD-761 system

controller only uses 32 address bits internally and

the address space wraps. Address 1 0000 0000 is

treated the same as 0 0000 0000.

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