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AMD-761 Datasheet(PDF) 71 Page - Advanced Micro Devices |
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AMD-761 Datasheet(HTML) 71 Page - Advanced Micro Devices |
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71 / 264 page  Chapter 2 AMD-761™ System Controller Programmer’s Interface 59 24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide Preliminary Information 17—16 Cyc_Per_Ref Cycles Per Refresh Refresh counter defines period of refresh requests. The following table shows the relationship between the values in this field and the resultant refresh period for the different system clock frequencies: 15–8 Reserved Reserved 7 CS7_X4Mode Chip-Select 7 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). 6 CS6_X4Mode Chip-Select 6 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). 5 CS5_X4Mode Chip-Select 5 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). 4 CS4_X4Mode Chip-Select 4 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). 3 CS3_X4Mode Chip-Select 3 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). 2 CS2_X4Mode Chip-Select 2 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). 1 CS1_X4Mode Chip-Select 1 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). 0 CS0_X4Mode Chip-Select 0 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). Bit Definitions (Continued) DRAM Mode/Status (Dev0:F0:0x58) Bit Name Function Value 66 MHz 100 MHz 133 MHz 00 30.72 µs 20.48 µs 15.36 µs 01 23.04 µs15.36 µs11.52 µs 10 15.36 µs10.24 µs 7.68 µs 11 7.68 µs 7.68 µs 3.84 µs |
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