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AMD-761 Datasheet(PDF) 88 Page - Advanced Micro Devices

Part # AMD-761
Description  AMD-761-TM System Controller Software/BIOS Design Guide
PDF  264 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AMD-761 Datasheet(HTML) 88 Page - Advanced Micro Devices

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76
AMD-761™ System Controller Programmer’s Interface
Chapter 2
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Preliminary Information
Programming Notes
13
Bypass_PLLs
Bypass PLLs
This bit is set for test and debug of the AMD-761™ system controller with the internal
PLLs disabled.
0 = AMD-761 system controller PLLs enabled
1 = AMD-761 system controller PLLs bypassed; clocks driven from SYSCLK and AGPCLK
pins directly to internal clock trees
12
Dis_Divider
Disable Divider
For internal test only.
11–8
Reserved
Reserved
7
SIP_ROM_En
SIP ROM Enabled
This bit indicates that the external SIP ROM is enabled and is read to create the SIP stream
to the AMD Athlon processor, instead of the internally generated SIP table.
6GP_Strap
General-Purpose Strap
This bit may be used as a general-purpose strap for communicating motherboard- specific
information to BIOS. The AMD-761 system controller does not use this strap internally.
5In_Clk_En
INCLK Enable
This bit indicates that the AMD-761 system controller delays the INCLK to the AMD Athlon
processor. When reset, the motherboard is expected to provide delay in the etch to center
the INCLK with the data.
4
Out_Clk_En
OUTCLK Enable
This bit indicates that the AMD Athlon processor delays the OUTCLK to the AMD-761
system controller. When reset, the motherboard is expected to provide delay in the etch to
center the OUTCLK with the data.
3–0
CPU0_Divider
CPU Divider
This bit field contains the CPU clock multiplier field supplied by the processor. Together
with the Clk_Speed field and the S2K0_Bus_Len field, these fields allow the AMD-761
system controller to properly program the AMD Athlon™ processor system bus
initialization logic using the SIP protocol.
The clock multiplier field is also known as the Frequency Identification (FID) bits and the
values are shown below.
Bit Definitions (Continued)
Config Status (Dev0:F0:0x88)
Bit
Name
Function
FID Value Multiplier FID Value Multiplier FID Value Multiplier FID Value Multiplier
0000
11.0
0100
5.0
1000
7.0
1100
9.0
0001
11.5
0101
5.5
1001
7.5
1101
9.5
0010
12.0
0110
6.0
1010
8.0
1110
10.0
0011
12.5
0111
6.5
1011
8.5
1111
10.5



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