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AMD-761 Datasheet(PDF) 67 Page - Advanced Micro Devices |
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AMD-761 Datasheet(HTML) 67 Page - Advanced Micro Devices |
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67 / 264 page  Chapter 2 AMD-761™ System Controller Programmer’s Interface 55 24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide Preliminary Information Programming Notes This register is not initialized at reset. BIOS must initialize all bits in this register prior to setting the SDRAM_Init bit (See “Bit Definitions DRAM Mode/Status (Dev0:F0:0x58)” on page 57) or attempting DRAM access for correct operation. The required settings for the wait state bits for SBP_Wait_State and Rd_Wait_State are listed in Table 8. 1–0 tRCD tRCD This bit field (tRCD) is the timing value (RAS to CAS latency, delay from activate to RD/WR command). 11 = 4 cycles 10 = 3 cycles (recommended “safe” configuration) 01 = 2 cycles 00 = 1 cycle Table 8. Wait State Settings for DRAM Timing Register DDR Interface Frequency SBP_Wait_State [Bit 31] Rd_Wait_State [Bit 28] 66 MHz 0 0 100 MHz 0 1 133 MHz 1 1 Bit Definitions (Continued) DRAM Timing (Dev0:F0:0x54) Bit Name Function |
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