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AMD-761 Datasheet(PDF) 40 Page - Advanced Micro Devices |
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AMD-761 Datasheet(HTML) 40 Page - Advanced Micro Devices |
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40 / 264 page ![]() 28 AMD-761™ System Controller Programmer’s Interface Chapter 2 AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Preliminary Information Reserved 0x68–0x6B Reserved 0x6C–0x6F Memory Status/Control 0x70–0x73 “Dev0:F0:0x70” on page 66 Reserved 0x74–0x77 Reserved 0x78–0x7B Reserved 0x7C–0x7F Reserved Boot Proc WHAMI 0x80–0x83 “Dev0:F0:0x80” on page 68 PCI Arbitration Control 0x84–0x87 “Dev0:F0:0x84” on page 70 Configuration Status 0x88–0x8B “Dev0:F0:0x88” on page 74 Reserved 0x8C–0x8F Reserved 0x90–0x93 Reserved 0x94–0x97 Reserved 0x98–0x9B PCI Top of Memory Reserved 0x9C–0x9F “Dev0:F0:0x9C” on page 77 AGP Capability Identifier 0xA0–0xA3 “Dev0:F0:0xA0” on page 79 AGP Status 0xA4–0xA7 “Dev0:F0:0xA4” on page 80 AGP Command 0xA8–0xAB “Dev0:F0:0xA8” on page 82 AGP Virtual Address Space Size 0xAC–0xAF “Dev0:F0:0xAC” on page 84 GART/AGP Mode Control 0xB0–0xB3 “Dev0:F0:0xB0” on page 86 AGP 4X Dynamic Compensation 0xB4–0xB7 “Dev0:F0:0xB4” on page 88 AGP Compensation Bypass 0xB8–0xBF “Dev0:F0:0xB8” on page 91 Memory Base Address 0 0xC0–0xC3 “Dev0:F0:0xC0” on page 95 Memory Base Address 1 0xC4–0xC7 “Dev0:F0:0xC4” on page 95 Table 6. Device 0, Function 0 Configuration Register Map (Continued) Host to PCI Bridge (Device 0, Function 0) Offset Reference |
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