AMD-761 datasheet(30/264 Pages) AMD

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AMD-761™ System Controller Programmer’s Interface

Chapter 2

AMD-761™ System Controller Software/BIOS Design Guide

24081D—February 2002

Preliminary Information

3. Memory range address decoding, send to AGP/PCI using

address bits [31:0] based on the following (for writes only

from the primary PCI):

•

Dev1:0x20, 0x24 (see “AGP/PCI Memory Limit and

Base

(Dev1:0x20)”

page 131

and

“AGP/PCI

Prefetchable Memory Limit and Base (Dev1:0x24)”

on page 133).

•

Dev

0:F0:0x84

AGP

VGA

BIOS

bits

(see

“Bit

Definitions PCI Arbitration Control (Dev0:F0:0x84)”

on page 71).

4. Else, the primary PCI is accessed (for writes only from the

AGP/PCI).

Note: GART

Control

access.

The

AMD-761

system

controller does not allow access to the memory-mapped

GART control registers from either PCI or AGP/PCI masters.

2.4

Configuration Registers

All functional registers in the AMD-761 system controller are

implemented as PCI configuration registers. The AMD-761

system controller implements a standard PCI hierarchy that

allows BIOS software to enumerate devices on the primary PCI,

the AGP port, and future interfaces. See the logical bus

hierarchy in Figure 3 on page 19.

Note that the AMD-761 system controller only responds to

function 0 and 1, device 0 and function 0, device 1. All other

configuration accesses return Fs. Function 1, device 0 accesses

are ignored unless enabled by the appropriate bit in the PCI

Control register (see “Dev0:F0:0x4C” on page 47).

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