AMD-761 datasheet(64/264 Pages) AMD

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AMD-761™ System Controller Programmer’s Interface

Chapter 2

AMD-761™ System Controller Software/BIOS Design Guide

24081D—February 2002

Preliminary Information

Bit Definitions

DRAM Timing (Dev0:F0:0x54)

Bit

Name

Function

SBP_Wait_State

Super Bypass Wait State

This bit forces a wait state on all super bypass reads. This bit should be set when the bus

speed is 133 MHz (refer to Table 8 on page 55).

0 = No additional wait state on super bypass reads

1 = Add wait state on super bypass reads

AddrTiming_A

Address Timing for Copy-A

This bit determines whether an extra delay is added to the address and command buses

(MAA[14:0], RASA#, CASA#; WEA#, CKEA, CS[5:4, 1:0]#). This bit should be programmed

depending on the loading presented to these pins.

0 = No extra delay

1 = XX ps delay

AddrTiming_B

Address Timing for Copy-B

This bit determines whether an extra delay is added to the address and command buses

(MAB[14:0], RASB#, CASB#; WEB#, CKEB, CS[7:6, 3:2]#). This bit should be programmed

depending on the loading presented to these pins.

0 = No extra delay

1 = XX ps delay

RD_Wait_State

Read Wait State

This bit determines whether a wait state must be added before returning the read data

from the memory to the requester. This bit should be programmed depending on the

overall round-trip timing.

Note that this bit must be set for 100-MHz and 133-MHz operation, but it must not be set

for 66-MHz operation (refer to Table 8).

0 = No wait states

1 = One wait state

Reg_DIMM_En

Registered DIMM Enable

This bit enables the use of registered DIMMs on the motherboard.

AMD-761™ system controller 0 = Unbuffered DIMMs

1 = Registered DIMMs

tWTR

Write Data In to Read Command Delay

This bit controls the number of clock cycles that must occur between the last valid write

operation and the next read command.

0 = tWTR duration is 1 clock cycle.

1 = tWTR duration is 2 clock cycles.

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